180nm_Oct2020/interfaces.mdwn

   1 # Interfaces for the 180nm Oct2020 ASIC
   2
   3 [List Link](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006355.html)
   4
   5 Bugreport and discussion at <https://bugs.libre-soc.org/show_bug.cgi?id=304>
   6
   7 These are bare minimum viability:
   8 These should be easily doable with LiteX.
   9
  10 * [[shakti/m_class/UART]]
  11 * [[shakti/m_class/I2C]]
  12 * [[shakti/m_class/GPIO]]
  13 * [[shakti/m_class/SPI]]
  14 * [[shakti/m_class/QSPI]]
  15 * [[shakti/m_class/LPC]]
  16 * [[shakti/m_class/EINT]]
  17 * [[shakti/m_class/JTAG]]
  18
  19 Under consideration:
  20
  21 * [[shakti/m_class/sdram]] see <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006374.html>
  22
  23 # Secondary priorities
  24
  25 * a pinmux
  26 * USB - again doable with LiteX. I'm talking to Enjoy Digital about what
  27   USB PHYs LiteX supports. - Yehowshua
  28 * SERDES for Ethernet - using LiteX and
  29   [Marvell PHY](https://www.mouser.com/ProductDetail/Marvell/88E1512-A0-NNP2I000?qs=vdi0iO8H4N0XzuXqBRxTqg%3D%3D)
  30 * Noting that a SERDES to RGMII PHY is $20 (kinda expensive for total cost
  31   of an SBC), we can instead do Eth over USB like the original RPI. This
  32   moves the complexity to software - could make doing eth things during
  33   boot loader a little more complex.
  34
  35 Jacob notes:
  36
  37 I haven't checked but I'm 99% sure that we will need to implement standard
  38 Power atomics, fences, ll/sc (including 128-bit version), cache flushes,
  39 and non-cacheable load/store operations if we want to support Linux on our
  40 october test chip.
  41
  42 <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006407.html>
  43
  44 ## Alternate USB Interface Options
  45  - https://github.com/im-tomu/valentyusb
  46  - https://github.com/lambdaconcept/lambdaUSB
  47  - https://github.com/greatscottgadgets/luna