2 auto-generated by [[pinouts.py]]
7 ## Bank N (32 pins, width 2)
9 | Pin | Mux0 | Mux1 | Mux2 | Mux3 |
10 | --- | ----------- | ----------- | ----------- | ----------- |
20 | 28 | N SYS_PLLCLK | |
21 | 29 | N SYS_PLLSELA0 | |
22 | 30 | N SYS_PLLSELA1 | |
23 | 31 | N SYS_PLLTESTOUT | |
25 ## Bank E (32 pins, width 2)
27 | Pin | Mux0 | Mux1 | Mux2 | Mux3 |
28 | --- | ----------- | ----------- | ----------- | ----------- |
29 | 32 | E SYS_PLLVCOUT | |
48 | 51 | E GPIOE_E10 | |
49 | 52 | E GPIOE_E11 | |
50 | 53 | E GPIOE_E12 | |
55 | 58 | E GPIOE_E13 | |
56 | 59 | E GPIOE_E14 | |
57 | 60 | E GPIOE_E15 | |
62 ## Bank S (32 pins, width 2)
64 | Pin | Mux0 | Mux1 | Mux2 | Mux3 |
65 | --- | ----------- | ----------- | ----------- | ----------- |
98 ## Bank W (32 pins, width 2)
100 | Pin | Mux0 | Mux1 | Mux2 | Mux3 |
101 | --- | ----------- | ----------- | ----------- | ----------- |
102 | 96 | W SDR_AD10 | |
103 | 97 | W SDR_AD11 | |
104 | 98 | W SDR_AD12 | |
105 | 99 | W SDR_DQM1 | |
112 | 106 | W SDR_D10 | |
113 | 107 | W SDR_D11 | |
114 | 108 | W SDR_D12 | |
115 | 109 | W SDR_D13 | |
116 | 110 | W SDR_D14 | |
117 | 111 | W SDR_D15 | |
118 | 112 | W SDR_CLK | |
119 | 113 | W SDR_CKE | |
120 | 114 | W SDR_RASn | |
121 | 115 | W SDR_CASn | |
122 | 116 | W SDR_WEn | |
123 | 117 | W SDR_CSn0 | |
128 | 122 | W UART0_TX | |
129 | 123 | W UART0_RX | |
130 | 124 | W MSPI0_CK | |
131 | 125 | W MSPI0_NSS | |
132 | 126 | W MSPI0_MOSI | |
133 | 127 | W MSPI0_MISO | |
135 # Pinouts (Fixed function)
139 auto-generated by [[pinouts.py]]
181 SPI Master 1 (general)
244 * SYS_PLLSELA0 : N29/0
245 * SYS_PLLSELA1 : N30/0
246 * SYS_PLLTESTOUT : N31/0
247 * SYS_PLLVCOUT : E0/0
299 # Pinmap for Libre-SOC 180nm
373 * SYS_PLLCLK 28 N28/0
374 * SYS_PLLSELA0 29 N29/0
375 * SYS_PLLSELA1 30 N30/0
376 * SYS_PLLTESTOUT 31 N31/0
377 * SYS_PLLVCOUT 32 E0/0
390 * MSPI0_NSS 125 W29/0
391 * MSPI0_MOSI 126 W30/0
392 * MSPI0_MISO 127 W31/0
438 ## Unused Pinouts (spare as GPIO) for 'Libre-SOC 180nm'
440 | Pin | Mux0 | Mux1 | Mux2 | Mux3 |
441 | --- | ----------- | ----------- | ----------- | ----------- |
442 | 64 | S VDDE_0 | | | |
443 | 65 | S VSSE_0 | | | |
444 | 66 | S VDDI_0 | | | |
445 | 67 | S VSSI_0 | | | |
446 | 86 | S VSSI_1 | | | |
447 | 87 | S VDDI_1 | | | |
448 | 88 | S VSSE_1 | | | |
449 | 89 | S VDDE_1 | | | |
450 | 100 | W VDDE_2 | | | |
451 | 101 | W VSSE_2 | | | |
452 | 102 | W VDDI_2 | | | |
453 | 103 | W VSSI_2 | | | |
454 | 118 | W VSSI_3 | | | |
455 | 119 | W VDDI_3 | | | |
456 | 120 | W VSSE_3 | | | |
457 | 121 | W VDDE_3 | | | |
459 # Reference Datasheets
461 datasheets and pinout links
463 * <http://datasheets.chipdb.org/AMD/8018x/80186/amd-80186.pdf>
464 * <http://hands.com/~lkcl/eoma/shenzen/frida/FRD144A2701.pdf>
465 * <http://pinouts.ru/Memory/sdcard_pinout.shtml>
466 * p8 <http://www.onfi.org/~/media/onfi/specs/onfi_2_0_gold.pdf?la=en>
467 * <https://www.heyrick.co.uk/blog/files/datasheets/dm9000aep.pdf>
468 * <http://cache.freescale.com/files/microcontrollers/doc/app_note/AN4393.pdf>
469 * <https://www.nxp.com/docs/en/data-sheet/MCF54418.pdf>
470 * ULPI OTG PHY, ST <http://www.st.com/en/interfaces-and-transceivers/stulpi01a.html>
471 * ULPI OTG PHY, TI TUSB1210 <http://ti.com/product/TUSB1210/>
473 # Pin Bank starting points and lengths