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  17 From: Staf Verhaegen <staf@fibraservi.eu>
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  58
  59 Luke Kenneth Casson Leighton schreef op wo 25-03-2020 om 15:53 [+0000]:
  60 > On Wed, Mar 25, 2020 at 1:46 PM Staf Verhaegen <staf@fibraservi.eu> wrote=
  61 :
  62 > a workaround (fallback position) is, we use DFF latches.  i created a"byp=
  63 ass latch" function which creates DFF latches with such acombinatorial bypa=
  64 ss: we actually use them quite a lot (includingbetween pipeline stages so t=
  65 hat we can programmatically cut the numberof pipeline stages in half at the=
  66  flick of a switch).
  67
  68 Would like to make separate side remark here. In ASICs MUXes are relative e=
  69 xpensive gates with respect to delay and power. So if this principle is gen=
  70 erally applied over the whole design it will make it difficult to make a ch=
  71 ip that is competitive in power/performance compared to ARM/x86 CPUs.
  72 In general if you are trying to optimize power/performance of your chip the=
  73  KISS (keep it simple stupid) is your friend. In that respect your complex =
  74 dual ISA decoder will have a power cost.
  75
  76 greets,
  77 Staf.
  78
  79
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