[libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline
[libre-riscv-dev.git] / 35 / 153847bbc0cdef791f38056dca25f0916ff06c
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14 Date: Sat, 21 Mar 2020 18:59:45 +0000
15 X-Bugzilla-Reason: CC
16 X-Bugzilla-Type: changed
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18 X-Bugzilla-Product: Libre-SOC's first SoC
19 X-Bugzilla-Component: Specification
20 X-Bugzilla-Version: unspecified
21 X-Bugzilla-Keywords:
22 X-Bugzilla-Severity: enhancement
23 X-Bugzilla-Who: mtnolan2640@gmail.com
24 X-Bugzilla-Status: CONFIRMED
25 X-Bugzilla-Resolution:
26 X-Bugzilla-Priority: ---
27 X-Bugzilla-Assigned-To: lkcl@lkcl.net
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30 Message-ID: <bug-186-13-E7CEglYNbE@http.bugs.libre-riscv.org/>
31 In-Reply-To: <bug-186-13@http.bugs.libre-riscv.org/>
32 References: <bug-186-13@http.bugs.libre-riscv.org/>
33 X-Bugzilla-URL: http://bugs.libre-riscv.org/
34 Auto-Submitted: auto-generated
35 MIME-Version: 1.0
36 Subject: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and
37 RISC-V
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