3d_gpu/architecture/decoder.mdwn

   1 # Decoder
   2
   3 The decoder is in charge of translating the RISCV or POWER instruction stream into operations that can be handled by our backend. It will have an extra input bit, set via a MSR that will switch which architecture it treats an instruction as.
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   5 ## POWER
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   7 ### Fixed point instructions
   8  - `addi`, `addis`, `mulli` - fairly straightforward - extract registers and immediate and translate to the appropriate op
   9  - `addic`, `addic.`, `subfic` - similar to above, but now carry needs to be saved somewhere
  10  - `add[o][.]`, `subf[o][.]`, `adde*`, `subfe*`, `addze*`, `neg*`, `mullw*`, `divw*` - These are more fun. They need to set the carry (if `.` is present) and overflow (if `o` is present) flags, as well as taking in the carry flag for the `e`xtended versions.
  11  - `addex` - uses the overflow flag as a carry in, and if `CY` is set to 1, sets overflow like it would carry.
  12  - `cmp`, `cmpi` - sets bits of the selected comparison result register based on whether the comparison result was greater than, less than, or equal to
  13  - `andi.`, `ori`, `andis.`, `oris`, `xori`, `xoris` - similar to above, though the `and` versions set the flags in `CR0`
  14  - `and*`, `or*`, `xor*`, `nand*`, `eqv*`, `andc*`, `orc*` - similar to the register-register arithmetic instructions above
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  18 ## RISCV