3d_gpu/architecture/dynamic_simd.mdwn

   1 # Dynamic Partitioned SIMD
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   3 To save hugely on gate count the normal practice of having separate scalar ALUs and separate SIMD ALUs is not followed.
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   5 Instead a suite of "partition points" identical in fashion to the Aspex Microelectronics ASP (Array-String-Architecture) architecture is deployed.
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   7 Basic principle: when all partition gates are open the ALU is subdivided into isolated and independent 8 bit SIMD ALUs.  Whenever any one gate is opened, the relevant 8 bit "part-results" are chained together in a downstream cascade to create 16 bit, 32 bit, 64 bit and 128 bit compound results.
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   9 Pages below describe the basic features of each and track the relevant bugreports.
  10
  11 * [[dynamic_simd/eq]]
  12 * [[dynamic_simd/gt]]
  13 * [[dynamic_simd/add]]
  14 * [[dynamic_simd/mul]]
  15 * [[dynamic_simd/shift]]