3d_gpu/architecture/memory_and_cache.mdwn

   1 # 180nm Test ASIC
   2
   3 This is a single-core, non-SMP, no analog PLLs, no clock-gating, test ASIC,
   4 expected to run at one-to-one from an external 24 mhz to 100 mhz clock.
   5
   6 The requirements are therefore **radically different** from the next
   7 roadmap ASIC.
   8
   9 Basic diagram:
  10
  11 [[!img 180nm_single_core_testasic_memlayout.jpg size="500x"]]
  12
  13 * Eight LD/ST Function Units with 2 ports each (one for aligned,
  14   one for misaligned), each connecting to one of a pair of L0
  15   Cache/Buffers.  Addr[4] determines which L0 Cache/Buffer to
  16   connect to.
  17
  18 * Twin L0 Cache/Buffers with only 16 128-bit-wide entries and
  19   a single-clock, single-path outgoing read **or** write protocol,
  20   with 16 (individual, non-multiplexed) incoming 128-bit entries.
  21
  22 * Each L0 Cache/Buffer connects by a single 128-bit data path
  23   to a standard non-SMP-aware L1 cache.  The data in and out
  24   is again read **or** write, 128-bit-wide.
  25
  26 * A pair of Wishbone "funnels" take the 128-bit requests, which include
  27   byte-level access lines, and *if needed* create a pair of 64-bit
  28   Wishbone-compliant requests.  "If needed", because if the lower
  29   half (or upper half) byte-level access lines are not set, then
  30   that indicates a 64-bit request, and thus only one request is needed.
  31   Only when byte-access lines in both upper and lower halves are set
  32   will two requests be needed
  33
  34 * Standard Wishbone 64-bit Bus.  This is where
  35   [Enjoy-Digital Litex](https://github.com/enjoy-digital/litex)
  36   code takes over, and connect to peripherals and testing infrastructure.
  37
  38 * Memory is the silicon-proven OpenCores [SDRAM|sdram] interface,
  39   and it is Wishbone compliant.
  40
  41 # 28-45nm Quad-Core SoC
  42
  43 This is full SMP, requires analog PLLs, clock gating, full SMP
  44 L1 and L2 cache coherency and atomic coherency.
  45
  46 ## Memory
  47
  48 TODO
  49
  50 ## Cache
  51
  52 TODO
  53
  54