3d_gpu/architecture/regfile.mdwn

   1 # Register Files
   2
   3 Discussion:
   4
   5 * <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008368.html>
   6
   7 A minimum of 4 register files are required for POWER:
   8
   9 * Floating-point
  10 * Integer
  11 * Control and Condition Code Registers (CR0-7)
  12 * SPRs (Special Purpose Registers)
  13 * Fast Registers (PC, MSR, CTR, LR, SRR0, SRR1 etc.)
  14
  15 Source code:
  16
  17 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/regfiles.py;hb=HEAD>
  18
  19 For a GPU, the FP and Integer registers need to be a massive 128 x 64-bit.
  20
  21 # Regfile groups, Port Allocations and bit-widths
  22
  23 * INT regfile: 32x 64-bit with 4R1W
  24 * SPR regfile: 1024x 64-bit (!) needs a "map" on that  1R1W
  25 * CR regfile:  8x 4-bit with full 8R8W (for full 32-bit read/write)
  26   - CR0-7: 4-bit
  27 * XER regfile: 2x 2-bit, 1x 1-bit with full 3R3W
  28   - CA(32) - 2-bit
  29   - OV(32) - 2-bit
  30   - SO     - 1 bit
  31 * FAST regfile: 7x 64-bit, full 3R2W (possibly greater)
  32   - MSR: 64-bit
  33   - PC: 64-bit
  34   - LR: 64-bit
  35   - CTR: 64-bit
  36   - TAR: 64-bit
  37   - SRR1: 64-bit
  38   - SRR2: 64-bit
  39
  40 # Connectivity between regfiles and Function Units
  41
  42 The target for the first ASICs is a minimum of 4 32-bit FMACs per clock cycle.
  43 If it is acceptable that this be achieved on sequentially-adjacent-numbered
  44 registers, a significant reduction in the amount of regfile porting may be
  45 achieved (down from 12R4W)
  46
  47 It does however require that the register file be broken into four
  48 completely separate and independent quadrants, each with their own
  49 separate and independent 3R1W (or 4R1W ports).
  50
  51 This then requires some Bus Architecture to connect and keep the pipelines
  52 busy.  Below is the connectivity diagram:
  53
  54 * A single Dynamic PartitionedSignal capable 64-bit-wide pipeline is at the
  55   top left and top right.
  56 * Multiple **pairs** of 32-bit Function Units (making up a 64-bit data
  57   path) connect, as "Concurrent Units", to each pipeline.
  58 * The number of **pairs** of Function Units **must** match (or preferably
  59   exceed) the number of pipeline stages.
  60 * Connected to each of the Operand and Result Ports on each Function Unit
  61   is a cyclic buffer.
  62 * Read-operands may "cycle" to reach their destination
  63 * Write-operands may be "cycled" so as to pick an appropriate destination.
  64 * **Independent** Common Data Buses, one for each Quadrant of the Regfile,
  65   connect between the Function Unit's cyclic buffers and the **global**
  66   cyclic buffers dedicated to that Quadrant.
  67 * Within each Quadrant's global cyclic buffers, inter-buffer transfer ports
  68   allow for copies of regfile data to be transferred from write-side to
  69   read-side.  This constitutes the entirety of what is known as an
  70   **Operand Forwarding Bus**.
  71 * **Between** each Quadrant's global cyclic buffers, there exists a 4x4
  72   Crossbar that allows data to move (slowly, and if necessary) across
  73   Quadrants.
  74
  75 Notes:
  76
  77 * There is only **one** 4x4 crossbar (or, one for reads, one for writes?)
  78   and thus only **one** inter-Quadrant 32-bit-wide data path (total
  79   bandwidth 4x32 bits).  These to be shared by **five** groups of
  80   operand ports at each of the Quadrant Global Cyclic Buffers.
  81 * The **only** way for register results and operands to cross over between
  82   quadrants of the regfile is that 4x4 crossbar.  Data transfer bandwidth
  83   being limited, the placement of an operation adversely affects its
  84   completion time.  Thus, given that read operands exceed the number
  85   of write operands, allocation of operations to Function Units should
  86   prioritise placing the operation where the "reads" may go straight
  87   through.
  88 * Outlined in this comment <https://bugs.libre-soc.org/show_bug.cgi?id=296#10>
  89   the infrastructure above can, by way of the cyclic buffers, cope with
  90   and automatically adapt between a *serial* delivery of operands, and
  91   a *parallel* delivery of operands.  And, that, actually, performance is
  92   not adversely affected by the serial delivery, although the latency
  93   of an FMAC is extended by 3 cycles: this being the fact that only one
  94   CDB is available to deliver operands.
  95
  96 Click on the image to expand it full-screen:
  97
  98 [[!img regfile_hilo_32_odd_even.png size="500px"]]
  99
 100 # Regspecs
 101
 102 * Source: <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/regspec.py;hb=HEAD>
 103
 104 "Regspecs" is a term used for describing the relationship between register files,
 105 register file ports, register widths, and the Computation Units that they connect
 106 to.
 107
 108 Regspecs are defined, in python, as follows:
 109
 110 | Regfile name | CompUnit Record name | bit range register mapping |
 111 | ----         | ----------           | ------------               |
 112 | INT          | ra                   | 0:3,5                      |
 113
 114 Description of each heading:
 115
 116 * Regfile name: INT corresponds to the INTEGER file, CR to Condition Register etc.
 117 * CompUnit Record name: in the Input or Output Record there will be a signal by
 118   name.  This field refers to that record signal, thus providing a sequential
 119   ordering for the fields.
 120 * Bit range: this is specified as an *inclusive* range of the form "start:end"
 121   or just a single bit, "N".  Multiple ranges may be specified, and are
 122   comma-separated.
 123
 124 Here is how they are used:
 125 ```
 126 class CRInputData(IntegerData):
 127     regspec = [('INT', 'a', '0:63'),      # 64 bit range
 128                ('INT', 'b', '0:63'),      # 6B bit range
 129                ('CR', 'full_cr', '0:31'), # 32 bit range
 130                ('CR', 'cr_a', '0:3'),     # 4 bit range
 131                ('CR', 'cr_b', '0:3'),     # 4 bit range
 132                ('CR', 'cr_c', '0:3')]     # 4 bit range
 133 ```
 134
 135 This tells us, when used by MultiCompUnit, that:
 136
 137 * CompUnit src reg 0 is from the INT regfile, is linked to CRInputData.a, 64-bit
 138 * CompUnit src reg 1 is from the INT regfile, is linked to CRInputData.b, 64-bit
 139 * CompUnit src reg 2 is from the CR regfile, is CRInputData.full\_cr, and 32-bit
 140 * CompUnit src reg 3 is from the CR regfile, is CRInputData.cr\_a, and 4-bit
 141 * CompUnit src reg 4 is from the CR regfile, is CRInputData.cr\_b, and 4-bit
 142 * CompUnit src reg 5 is from the CR regfile, is CRInputData.cr\_c, and 4-bit
 143
 144 Likewise there is a corresponding regspec for CROutputData.  The two are combined
 145 and associated with the Pipeline:
 146
 147 ```
 148 class CRPipeSpec(CommonPipeSpec):
 149     regspec = (CRInputData.regspec, CROutputData.regspec)
 150     opsubsetkls = CompCROpSubset
 151 ```
 152
 153 In this way the pipeline can be connected up to a generic, general-purpose class
 154 (MultiCompUnit), which would otherwise know nothing about the details of the ALU
 155 (Pipeline) that it is being connected to.
 156
 157 In addition, on the other side of the MultiCompUnit, the regspecs contain enough
 158 information to be able to wire up batches of MultiCompUnits (now known, because
 159 of their association with an ALU, as FunctionUnits), associating the MultiCompUnits
 160 correctly with their corresponding Register File.
 161
 162 Note: there are two exceptions to the "generic-ness and abstraction"
 163 where MultiCompUnit "knows nothing":
 164
 165 1. When the Operand Subset has a member "zero_a".  this tells MultiCompUnit
 166    to create a multiplexer that, if operand.zero_a is set, will put **ZERO**
 167    into its first src operand (src_i[0]) and it will **NOT** put out a
 168    read request (**NOT** raise rd.req[0]) for that first register.
 169 2. When the Operand Subset has a member "imm_data".  this tells
 170    MultiCompUnit to create a multiplexer that, if operand.imm_data.ok is
 171    set, will copy operand.imm_data into its *second* src operand (src_i[1]).
 172    Further: that it will **NOT** put out a read request (**NOT** raise
 173    rd.req[1]) for that second register.
 174
 175 These should only be activated for INTEGER and Logical pipelines, and
 176 the regspecs for them must note and respect the requirements: input
 177 regspec[0] may *only* be associated with operand.zero_a, and input
 178 regspec[1] may *only* be associated with operand.imm_data.  the POWER9
 179 Decoder and the actual INTEGER and Logical pipelines have these
 180 expectations **specifically** hard-coded into them.