3d_gpu/architecture/tomasulo_transformation.mdwn

   1 # Conversion from Tomasulo to Scoreboards
   2
   3 See [discussion (1)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006747.html) and
   4 [discussion (2)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006904.html)
   5
   6 This page aids and assists in understanding the full functional equivalence
   7 of a Scoreboard-based design when compared to a Tomasulo algorithm.  However
   8 it is extremely important to note that the Academic literature, by focussing
   9 exclusively on the published patent covering Q-Tables, is hopelessly inaccurate,
  10 factually incorrect and completely misleading.
  11
  12 By only comparing Q-Tables against the entirety of the Tomasulo algorithm,
  13 this is equivalent to narrowly focussing on the Reorder Buffer of
  14 Tomasulo, excluding all else, and concluding that a design that uses a
  15 ROB and therefore the entire Tomasulo algorithm itself is incapable of useful
  16 high-performance out-of-order execution.
  17
  18 This article helps readers to understand that Q-Tables != Scoreboards,
  19 by describing a series of functionally-equivalent transformations that,
  20 when followed, *turn* the Tomasulo algorithm *into* a Scoreboard-based
  21 design.  It also highlights that, following that transformation, multi-issue
  22 execution is near-trivial to add by comparison. Precise exception
  23 handling is also trivial to add (holding of write commits) and is
  24 described in the [[6600scoreboard]] page under "Shadowing"
  25
  26 > This is a very intricate and complicated subject matter for sure.
  27
  28 yes, except it doesn't have to be.  the actual
  29 <https://en.wikipedia.org/wiki/Levenshtein_distance> between Tomasulo and
  30 6600 really is not that great.
  31
  32 i thought it would be fun to use a new unpronounceable word i learned
  33 yesterday :)
  34
  35 > At some point, it be great to really break things down and make them
  36 > more accessible.
  37
  38 yes. it comes down to time.
  39
  40 start with this.
  41
  42 1. Begin from Tomasulo.
  43
  44 2. Make sure to add an Operand Forwarding Bus.  this is critical to
  45    providing the functionality provided by the Tomasulo Common Data Bus.
  46
  47    note (later) that multiple Op Fwd Buses may be conveniently added
  48    as parallel data paths without severe design penalties.
  49
  50 3. Start by only allowing one row per Reservation Station.
  51
  52 4. Expand the number of RSes so that if you were to count the total
  53    number of places operands are stored, they are the same.
  54
  55    (another way to put this is, "flatten all 2D RSes into 1D")
  56
  57 5. where pipelines were formerly connected exclusively to one RS,
  58    *preserve* those connections even though the rows are now 1D flattened.
  59
  60    (another way to put this is: we have a global 1D naming scheme to
  61    reference the *operand latches* rather than a 2D scheme involving RS
  62    number in 1 dimension and the row number in the 2nd)
  63
  64 6. give this 1D flattening an UNARY numbering scheme.
  65
  66 7. make the size of the Reorder Buffer EXACTLY equal to the number of
  67    1D flattened RSes.
  68
  69 8. rename RSes to "Function Units" (actually in Thornton's book the phrase
  70    "Computation Units" is used)
  71
  72    thus, at this point in the transformation, the ROB row number *IS*
  73    the Function Unit Number, the need to actually store the ROB # in the
  74    Reservation Station Row is REMOVED, and consequently the Reservation
  75    Stations are NO LONGER A CAM.
  76
  77 9. give all register file numbers (INT FP) an UNARY numbering.
  78
  79    this means that in the ROB, updating of register numbers in a multi-issue
  80    scenario is a matter of raising one of any number of single bits.
  81    contrast this in the Tomasulo to having to multi-port the SRAM in the
  82    ROB, setting multiple bits *even for single-issue* (5-bits for 32-bit reg
  83    numbering).
  84
  85 10. add "Shadowing" capability to each Function Unit
  86     and create a Shadow Matrix (appx 20 gates per Function Unit)
  87
  88     (the "Shadow" capability hooks into the WRITE-COMMIT phase of every
  89     Function Unit, permitting it to EXECUTE but prohibiting it from WRITING
  90     the result of that execution until explicitly permitted to do so).
  91
  92 11. Upgrade the CDB from a multi-fan-in, multi-fan-out, single resource
  93     global choke-point to **separate** (multiple, if desired) read-fanout
  94     broadcast and write-fan-in register data broadcast buses.
  95
  96 # Post-transformation Analysis
  97
  98 with the ROB now having rows of bitvectors, it is now termed a "Matrix".
  99
 100 the left side of the ROB, which used to contain the RS Number in unary,
 101 now contains a *bitvector* Directed Acyclic Graph of the FU to FU
 102 dependencies, and is split out into its own Matrix.
 103
 104 this we call the FU-FU Dependency Matrix.
 105
 106 therefore, where previously, it was the ROB Row binary number that preserved
 107 instruction order (as an inherent DAG through sequential cyclically-incremented
 108 numbering), the 2-D bit-level FU-FU matrix preserves the same DAG by way of
 109 single-bit cells that express FU-to-FU dependencies, creating a hardware-form
 110 of a software "linked list".
 111
 112 the remainder of the "ROB" contains the register numbers in unary Matrix
 113 form, and with each row being directly associated with a Function Unit,
 114 we now have an association between FU and Regs which preserves the
 115 knowledge of what instruction required which registers, *and* who will
 116 produce the result.
 117
 118 this we call the FU-Regs Dependency Matrix.
 119
 120 that *really is it*.
 121
 122 take some time to absorb the transformation which not only preserves
 123 absolutely every functional aspect of the Tomasulo Algorithm, it
 124 drastically simplifies the implementation, reduces gate count, reduces
 125 power consumption *and* provides a strong foundation for doing arbitrary
 126 multi-issue execution with only an O(N) linear increase in gate count
 127 to do so.
 128
 129 further hilariously simple additional transformations occur to replace
 130 former massive resource constrained bottlenecks, due to the binary
 131 numbering on both ROB numbers and Reg numbers, with simple large unary
 132 NOR gates:
 133
 134 * the determination of when hazards are clear, on a per register basis,
 135   is a laughably trivial NOR gate across all columns of the FU-REGs matrix,
 136   producing a row bitvector for each read register and each write register.
 137
 138 * the determination of when a Function Unit may proceed is a laughably
 139   trivial NOR gate across all *rows* of the *FU-FU* Matrix, producing a
 140   row-based vector, determining that it is "readable" if there exists no
 141   write hazard and "writable" if there exists no read hazard.
 142
 143 * the Tomasulo Common Data Bus, formerly being a single chokepoint
 144   binary-addressing global Bus, may now be upgraded to *MULTIPLE* Common
 145   Data Buses that, because the addressing information about registers is now
 146   in unary, is likewise laughably trivial to use cascading Priority Pickers
 147   (a nmigen PriorityEncoder and Decoder, back-to-back) to determine which
 148   Function Unit shall be granted access to which CDB in order to receive
 149   (or send) its operand (or result).
 150
 151 * multi-issue as i mentioned a few times is an equally laughably trivial
 152   matter of transitively cascading the Register Dependency Hazards (both
 153   read and write) across future instructions in the same multi issue
 154   execution window. instr2 has instr1 AND instr2's hazards.  instr3 has
 155   instr1 AND instr2 AND instr3's hazards and so on.  this just leaves
 156   the necessity of increasing register port numbers, number of CDBs,
 157   and LD/ST memory bandwidth to compensate and cope with the additional
 158   resource demands that will now occur.
 159
 160 the latter is particularly why we have a design that, ultimately, we
 161 could take on ARM, Intel, and AMD.
 162
 163 there is no reason technically why we could not do a 4, 6 or 8 multi
 164 issue system, and with enough Function Units and the cyclic buffer system
 165 (so as not to require a full crossbar at the Common Data Buses), and
 166 proper stratification and design of the register files, massive Vector
 167 parallelism at the pipelines would be kept fully occupied without an
 168 overwhelming increase in gates or power consumption that would normally
 169 be expected, and scalar performance would be similarly high as well.
 170
 171 # Terminology notes
 172
 173 These terms help understand that conceptually there is no difference
 174 in the capabilities of Tomasulo and Scoreboards.
 175
 176 | Tomasulo name            | Scoreboard name                              |
 177 | -----                    | ----                                         |
 178 | Precise Exceptions       | Precise-capable ("Shadowed") Scoreboard      |
 179 | ROB index cycling order  | FU-FU DAG that preserves instruction order   |
 180 | Reorder Buffer           | hybrid of Shadow, FU-FU and FU-Regs Matrices |
 181 | Reservation Station CAMs | RS Row = "Computation Unit latches" (no CAM) |
 182 | "register renaming"      | "nameless" registers (Comp Unit latches)     |
 183 | part-ROB, part-RS        | Q-Tables                                     |
 184 | blocking Common Data Bus | fan-out Read Reg, fan-in Write, OpFwd Bus(es)|
 185 | Centralised regfile(s)   | Centralised regfile(s)                       |