3d_gpu/architecture/tomasulo_transformation.mdwn

   1 # Conversion from Tomasulo to Scoreboards
   2
   3 See [discussion](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006747.html).
   4 This page aids and assists in understanding the full functional equivalence
   5 of a Scoreboard-based design when compared to a Tomasulo algorithm.  However
   6 it is extremely important to note that the Academic literature, by focussing
   7 exclusively on the published patent covering Q-Tables, is hopelessly inaccurate,
   8 factually incorrect and completely misleading.
   9
  10 By only comparing Q-Tables against the entirety of the Tomasulo algorithm,
  11 this is equivalent to narrowly focussing on the Reorder Buffer of
  12 Tomasulo, excluding all else, and concluding that a design that uses a
  13 ROB is incapable of useful high-performance out-of-order execution.
  14
  15 This article helps readers to understand that Q-Tables != Scoreboards,
  16 by describing a series of functionally-equivalent transformations that,
  17 when followed, *turn* the Tomasulo algorithm *into* a Scoreboard-based
  18 design.
  19
  20 On Saturday, May 16, 2020, Yehowshua <yimmanuel3@gatech.edu> wrote:
  21 > This is a very intricate and complicated subject matter for sure.
  22
  23 yes, except it doesn't have to be.  the actual
  24 <https://en.wikipedia.org/wiki/Levenshtein_distance> between Tomasulo and
  25 6600 really is not that great.
  26
  27 i thought it would be fun to use a new unpronounceable word i learned
  28 yesterday :)
  29
  30 > At some point, it be great to really break things down and make them
  31 > more accessible.
  32
  33 yes. it comes down to time.
  34
  35 start with this.
  36
  37 1. Begin from Tomasulo.  neither TS nor original 6600 have precise
  38    exceptions so we leave that out for now.
  39
  40 2. Make sure to add an Operand Forwarding Bus.  this is critical to
  41    providing the functionality provided by the Tomasulo Common Data Bus.
  42
  43    note (later) that multiple Op Fwd Buses may be conveniently added
  44    as parallel data paths without severe design penalties.
  45
  46 3. Start by only allowing one row per Reservation Station.
  47
  48 4. Expand the number of RSes so that if you were to count the total
  49    number of places operands are stored, they are the same.
  50
  51    (another way to put this is, "flatten all 2D RSes into 1D")
  52
  53 5. where pipelines were formerly connected exclusively to one RS,
  54    *preserve* those connections even though the rows are now 1D flattened.
  55
  56    (another way to put this is: we have a global 1D naming scheme to
  57    reference the *operand latches* rather than a 2D scheme involving RS
  58    number in 1 dimension and the row number in the 2nd)
  59
  60 6. give this 1D flattening an UNARY numbering scheme.
  61
  62 7. make the size of the Reorder Buffer EXACTLY equal to the number of
  63    1D flattened RSes.
  64
  65 8. rename RSes to "Function Units" (actually in Thornton's book the phrase
  66    "Computation Units" is used)
  67
  68    thus, at this point in the transformation, the ROB row number *IS*
  69    the Function Unit Number, the need to actually store the ROB # in the
  70    Reservation Station Row is REMOVED, and consequently the Reservation
  71    Stations are NO LONGER A CAM.
  72
  73 9. give all register file numbers (INT FP) an UNARY numbering.
  74
  75    this means that in the ROB, updating of register numbers in a multi-issue
  76    scenario is a matter of raising one of any number of single bits.
  77    contrast this in the Tomasulo to having to multi-port the SRAM in the
  78    ROB, setting multiple bits *even for single-issue* (5-bits for 32-bit reg
  79    numbering).
  80
  81 with the ROB now having rows of bitvectors, it is now termed a "Matrix".
  82
  83 the left side of the ROB, which used to contain the RS Number in unary,
  84 now contains a *bitvector* Directed Acyclic Graph of the FU to FU
  85 dependencies, and is split out into its own Matrix.
  86
  87 this we call the FU-FU Dependency Matrix.
  88
  89 therefore, where previously, it was the ROB Row binary number that preserved
  90 instruction order (as an inherent DAG through sequential cyclically-incremented
  91 numbering), the 2-D bit-level FU-FU matrix preserves the same DAG by way of
  92 single-bit cells that express FU-to-FU dependencies, creating a hardware-form
  93 of a software "linked list".
  94
  95 the remainder of the "ROB" contains the register numbers in unary Matrix
  96 form, and with each row being directly associated with a Function Unit,
  97 we now have an association between FU and Regs which preserves the
  98 knowledge of what instruction required which registers, *and* who will
  99 produce the result.
 100
 101 this we call the FU-Regs Dependency Matrix.
 102
 103 that *really is it*.
 104
 105 take some time to absorb the transformation which not only preserves
 106 absolutely every functional aspect of the Tomasulo Algorithm, it
 107 drastically simplifies the implementation, reduces gate count, reduces
 108 power consumption *and* provides a strong foundation for doing arbitrary
 109 multi-issue execution with only an O(N) linear increase in gate count
 110 to do so.
 111
 112 further hilariously simple additional transformations occur to replace
 113 former massive resource constrained bottlenecks, due to the binary
 114 numbering on both ROB numbers and Reg numbers, with simple large unary
 115 NOR gates:
 116
 117 * the determination of when hazards are clear, on a per register basis,
 118   is a laughably trivial NOR gate across all columns of the FU-REGs matrix,
 119   producing a row bitvector for each read register and each write register.
 120
 121 * the determination of when a Function Unit may proceed is a laughably
 122   trivial NOR gate across all *rows* of the *FU-FU* Matrix, producing a
 123   row-based vector, determining that it is "readable" if there exists no
 124   write hazard and "writable" if there exists no read hazard.
 125
 126 * the Tomasulo Common Data Bus, formerly being a single chokepoint
 127   binary-addressing global Bus, may now be upgraded to *MULTIPLE* Common
 128   Data Buses that, because the addressing information about registers is now
 129   in unary, is likewise laughably trivial to use cascading Priority Pickers
 130   (a nmigen PriorityEncoder and Decoder, back-to-back) to determine which
 131   Function Unit shall be granted access to which CDB in order to receive
 132   (or send) its operand (or result).
 133
 134 * multi-issue as i mentioned a few times is an equally laughably trivial
 135   matter of transitively cascading the Register Dependency Hazards (both
 136   read and write) across future instructions in the same multi issue
 137   execution window. instr2 has instr1 AND instr2's hazards.  instr3 has
 138   instr1 AND instr2 AND instr3's hazards and so on.  this just leaves
 139   the necessity of increasing register port numbers, number of CDBs,
 140   and LD/ST memory bandwidth to compensate and cope with the additional
 141   resource demands that will now occur.
 142
 143 the latter is particularly why we have a design that, ultimately, we
 144 could take on ARM, Intel, and AMD.
 145
 146 there is no reason technically why we could not do a 4, 6 or 8 multi
 147 issue system, and with enough Function Units and the cyclic buffer system
 148 (so as not to require a full crossbar at the Common Data Buses), and
 149 proper stratification and design of the register files, massive Vector
 150 parallelism at the pipelines would be kept fully occupied without an
 151 overwhelming increase in gates or power consumption that would normally
 152 be expected, and scalar performance would be similarly high as well.