1 # Coriolis2 180nm layout
3 * <http://bugs.libre-riscv.org/show_bug.cgi?id=138> - toplevel
4 * <http://bugs.libre-riscv.org/show_bug.cgi?id=199> - main layout
5 * <https://ftp.libre-soc.org/course_18oct2021/>
10 [[!img simple_floorplan.png size="500x"]]
14 There are 5 register files: SPR, INT, CR, XER and FAST.
16 Access to each of the ports is managed via a "Priority Picker" - an
17 unary-in but one-hot unary-out picker - which allows one and only one
18 "user" of a given regfile port at any one time.
22 There are 8 Function Units: ALU, Logical, Condition, Branch, ShiftRot, LDST,
25 Each Function Unit has operand inputs and operand outputs. Across *all*
26 pipelines there are multiple Function Units that require "RA" (Register A
27 Integer Register File). All of such "RA" read requests are (surprise)
28 connected to the same "Priority Picker" mentioned above: likewise
29 all Function Units requiring write to the "RT" register are connected
30 to the exact same "RT-managing" Write Priority Picker.
32 ### Load Store Computation Unit(s)
34 Load/Store is a special type of Computation Unit that additionally has
35 access to external memory. In the case where multiple LDSTCompUnits
36 are added, L0CacheBuffer is responsible for "merging" these into single
39 There are however *two* L0 Caches (both 128-bit wide), with a split
40 on address bit 4 for selecting either the odd L0 Cache or the even L0 Cache.
42 Each of the two L0 caches has dual 64-bit Wishbone interfaces giving
43 a total of *four* 64-bit Memory Bus requests that will be merged through
44 an Arbiter down onto the same Memory Bus that the I-Cache is also connected
49 Instructions are decoded by PowerDecoder2, after being read by the
50 simple core FSM from the Instruction Cache. Currently this is an
51 extremely simple memory block, to be replaced by a proper I-Cache
52 with a proper connection to the Memory Bus (wishbone).
56 The IO Ring is autogenerated from the same pinmux program
57 that created the [[180nm_Oct2020/pinouts]] and the SVG
58 image. The image was used by Greatek for packaging as well as
59 a PCB designed by Professor Galayko of Sorbonne University.
61 The exact same pinmux program's output, specifying all interfaces,
62 was also used to autogenerate the HDL for the JTAG Boundary Scan.
64 By strictly using the exact same *machine readable* specification
65 for all Interfaces using only autogenerated techniques it was possible
66 to ensure complete consistency across
69 * SVG Image for packaging
75 [[!img 180nm_Oct2020/ls180.svg size="400x" ]]
79 To build see [[HDL_workflow/coriolis2]]. A tag has been used and the
80 build instructions specify it. The soclayout repository is standalone,
81 containing a snapshot of the verilog autogenerated output.
85 There are several talks online now.
87 * [[conferences/fosdem2022]]
88 * <https://m.youtube.com/playlist?list=PLBtNqZjUZB80uByfZVm0gGYEtmTG0mZzm>