3d_gpu/layouts/coriolis2_180nm.mdwn

   1 # Coriolis2 180nm layout
   2
   3 * <http://bugs.libre-riscv.org/show_bug.cgi?id=138> - toplevel
   4 * <http://bugs.libre-riscv.org/show_bug.cgi?id=199> - main layout
   5
   6 # Simple floorplan
   7
   8 [[!img simple_floorplan.png]]
   9
  10 ## Register files
  11
  12 There are 5 register files: SPR, INT, CR, XER and FAST.
  13
  14 Access to each of the ports is managed via a "Priority Picker" - an
  15 unary-in but one-hot unary-out picker - which allows one and only one
  16 "user" of a given regfile port at any one time.
  17
  18 ## Computation Units
  19
  20 There are 8 Function Units: ALU, Logical, Condition, Branch, ShiftRot, LDST,
  21 Trap, and SPRs.
  22
  23 Each Function Unit has operand inputs and operand outputs.  Across *all*
  24 pipelines there are multiple Function Units that require "RA" (Register A
  25 Integer Register File).  All of such "RA" read requests are (surprise)
  26 connected to the same "Priority Picker" mentioned above: likewise
  27 all Function Units requiring write to the "RT" register are connected
  28 to the exact same "RT-managing" Write Priority Picker.
  29
  30 ### Load Store Computation Unit(s)
  31
  32 Load/Store is a special type of Computation Unit that additionally has
  33 access to external memory.  In the case where multiple LDSTCompUnits
  34 are added, L0CacheBuffer is responsible for "merging" these into single
  35 requests.
  36
  37 There are however *two* L0 Caches (both 128-bit wide), with a split
  38 on address bit 4 for selecting either the odd L0 Cache or the even L0 Cache.
  39
  40 Each of the two L0 caches has dual 64-bit Wishbone interfaces giving
  41 a total of *four* 64-bit Memory Bus requests that will be merged through
  42 an Arbiter down onto the same Memory Bus that the I-Cache is also connected
  43 to.
  44
  45 ## Instructions
  46
  47 Instructions are decoded by PowerDecoder2, after being read by the
  48 simple core FSM from the Instruction Cache.  Currently this is an
  49 extremely simple memory block, to be replaced by a proper I-Cache
  50 with a proper connection to the Memory Bus (wishbone).
  51