3d_gpu/microarchitecture.mdwn

   1 # High-level architectural Requirements
   2
   3 * SMP Cache coherency (TileLink?)
   4 * Minumum 800mhz
   5 * Minimum 2-core SMP, more likely 4-core uniform design,
   6   each core with full 4-wide SIMD-style predicated ALUs
   7 * 6GFLOPS single-precision FP
   8 * 128 64-bit FP and 128 64-bit INT register files
   9 * RV64GC compliance
  10 * 4-lane 1Rx1W SRAMs for registers numbered 32 and above;
  11   Multi-R x Multi-W for registers 1-31.
  12   TODO: consider 2R for registers to be used as predication targets
  13   if >= 32.
  14
  15 # Conversation Notes
  16
  17 ----
  18
  19 'm thinking about using tilelink (or something similar) internally as
  20 having a cache-coherent protocol is required for implementing Vulkan
  21 (unless you want to turn off the cache for the GPU memory, which I
  22 don't think is a good idea), axi is not a cache-coherent protocol,
  23 and tilelink already has atomic rmw operations built into the protocol.
  24 We can use an axi to tilelink bridge to interface with the memory.
  25
  26 I'm thinking we will want to have a dual-core GPU since a single
  27 core with 4xSIMD is too slow to achieve 6GFLOPS with a reasonable
  28 clock speed. Additionally, that allows us to use an 800MHz core clock
  29 instead of the 1.6GHz we would otherwise need, allowing us to lower the
  30 core voltage and save power, since the power used is proportional to
  31 F\*V^2. (just guessing on clock speeds.)
  32
  33 ----
  34
  35 I don't know about power, however I have done some research and a 4Kbyte
  36 (or 16, icr) SRAM (what I was thinking of for a tile buffer) takes in the
  37 ballpark of 1000 um^2 in 28nm.
  38 Using a 4xFMA with a banked register file where the bank is selected by the
  39 lower order register number means we could probably get away with 1Rx1W
  40 SRAM as the backing memory for the register file, similarly to Hwacha. I
  41 would suggest 8 banks allowing us to do more in parallel since we could run
  42 other units in parallel with a 4xFMA. 8 banks would also allow us to clock
  43 gate the SRAM banks that are not in use for the current clock cycle
  44 allowing us to save more power. Note that the 4xFMA could be 4 separately
  45 allocated FMA units, it doesn't have to be SIMD style. If we have enough hw
  46 parallelism, we can under-volt and under-clock the GPU cores allowing for a
  47 more efficient GPU. If we are using the GPU cores as CPU cores as well, I
  48 think it would be important to be able to use a faster clock speed when not
  49 using the extended registers (similar to how Intel processors use a lower
  50 clock rate when AVX512 is in use) so that scalar code is not slowed down
  51 too much.
  52
  53 > > Using a 4xFMA with a banked register file where the bank is selected by
  54 > the
  55 > > lower order register number means we could probably get away with 1Rx1W
  56 > > SRAM as the backing memory for the register file, similarly to Hwacha.
  57 >
  58 >  okaaay.... sooo... we make an assumption that the top higher "banks"
  59 > are pretty much always going to be "vectorised", such that, actually,
  60 > they genuinely don't need to be 6R-4W (or whatever).
  61 >
  62 Yeah pretty much, though I had meant the bank number comes from the
  63 least-significant bits of the 7-bit register number.