3d_gpu/tutorial.mdwn

   1 # Tutorial on how to get into LibreSOC development
   2
   3 This tutorial is a guide for anyone wishing, literally, to start from scratch and learn how to contribute to the LibreSOC.  Much of this you should go through (skim and extract) the [[HDL_workflow]] document, however until you begin to participate much of that document is not fully relevant. This one is intended to get you "up to speed" with basic concepts.
   4
   5 # Programming vs hardware.
   6
   7 We are assuming here you know some programming language.  You know that it works in sequence (unless you went to Imperial College in the 80s and have heard of [Parlog](https://en.m.wikipedia.org/wiki/Parlog)).
   8
   9 Hardware basically comprises transistor circuits. There's nothing in the universe or the laws of physics that says light and electricity have to operate sequentially, and consequently all Digital ASICs are an absolutely massive arrays of unbelievably excruciatingly tediously low level "gates", in parallel, separated occasionally by clock-synchronised "latches" that capture data from one processing section before passing it on to the next.
  10
  11 ASIC designers avoid going completely off their heads at the level of detail involved by "compartmentalising" designs into a huge hierarchy of modular design, where the tools selected aid and assist in isolating as much of the contextually-irrelevant detail as practical, allowing the developer to think in relevant concepts without being overwhelmed.
  12
  13 Understanding this is particularly important because the level of hierarchy of design may be *one hundred* or more modules deep *just in nmigen alone*, (and that's before understanding the abstraction that nmigen itself provides); yosys goes through several layers as well, and finally, alliance / corilolis2 have their own separate layers.
  14
  15 Throughout each layer, the abstractions of a higher layer are removed and replaced with topologically-equivalent but increasingly detailed equivalents.  nmigen has the *concept* of integers (not really: it has the concept of something that, when the tool is executed, will create a representation *of* an integer), and this is passed through intact to yosys.  yosys however knows that integers need to be replaced by wires, buses and gates, so that's what it does.
  16
  17 Thus, you can think safely in terms of "integers" when designing and writing the HDL, confident that the details of converting to gates and wires is taken care of.
  18
  19 # Debian
  20
  21 Sorry, ubuntu, macosx and windows lovers: start by installing debian either in actual hardware or in a VM.  A VM has the psychological disadvantage of making you feel like you are not taking things seriously (it's a toy), so consider dual booting or getting a second machine.
  22
  23 # Python
  24
  25 First: learn python.  python3 to be precise.  Start by learning the basic data types: string, int, float then dict, list and tuple.  Then move on to functions, then classes, exceptions and the "with" statement.  Along the way you will pick up imports. Do not use "import *" it will cause you a world of pain.
  26
  27 # Git
  28
  29 Git is essential.  look up git workflow: clone, pull, push, add, commit.  Create some test repos and get familiar with it. Read the [[HDL_workflow]] document.
  30
  31 # Basics of gates
  32
  33 You need to understand what gates are.  look up AND, OR, XOR, NOT, NAND, NOR, MUX, DFF, SR latch on electronics forums and wikipedia. also look up "register latches", then HALF ADDER and FULL ADDER.  ASIC designers call these "Cells".  There are some more complex "Cells" such as "4-input MUX" or "3-input XOR" and so on, which should be self-explanatory.
  34
  35 Also look up "boolean algebra", "Karnaugh maps", truth tables and things like that.
  36
  37 From there you can begin to appreciate how deeply ridiculously low level this all is, and why we are using nmigen.  nmigen constructs "useful" concepts like "32 bit numbers", which actually do not exist at the gate level: they only exist by way of being constructed from chains of 1 bit (binary) processing!
  38
  39 So for example, a 32 bit adder is "constructed" from a batch of 32 FULL ADDERs (actually, 31 FULL and one HALF).  Even things like comparing two numbers, the simple "==" or ">=" operators, are done entirely with a bit-level cascade!
  40
  41 This would drive you nuts if you had to think at this level all the time, consequently "High" in "High Level Language" was invented. Luckily in python, you can override \_\_add\_\_ and so on in order that when you put "a + b" into a nmigen program it gives you the *impression* that two "actual" numbers are being added, whereas in fact you requested that the HDL create a massive bunch of "gates" on your behalf.
  42
  43 i.e. *behind the scenes* the HDL uses "cells" that in a massive hierarchical cascade ultimately end up at nothing more than "gates".
  44
  45 Yes you really do need to know this because those "gates" cost both power, space, and take time to switch.  So if you have too many of them in a chain, your chip is limited in its top speed.  This is the point at which you should be looking up "pipelines" and "register latches", as well as "combinatorial blocks".
  46
  47 you also want to look up the concept of a FSM (Finite State Machine) and the difference between a Mealy and a Moore FSM.
  48
  49 # nmigen
  50
  51 once you understand gates and python, nmigen starts to make sense.
  52
  53 nmigen works by creating an in-memory "Abstract Syntax Tree" which is handed to yosys (via yosys "ILANG" format) which in turn actually generates the cells and netlists.
  54
  55 so you write code in python, using the nmigen library of classes and helper routines, to construct an AST which *represents* the actual hardware. yosys takes care of the level *below* nmigen, and is just a tool.
  56
  57 install nmigen (and yosys) by following [[HDL_workflow]] then follow the excellent tutorial by Robert <https://github.com/RobertBaruch/nmigen-tutorial>
  58
  59 pay particular attention to the bits in HDL workflow about using yosys "show" command.  this is essential because the nmigen code gets turned into gates, and yosys show will bring up a graph that allows you to see that.
  60
  61 pay particular attention to "comb" (combinatorial) and "sync" (synchronous).  comb is a sequence of gates without any clock-synxhronised latches.  "sync" will *automatically* create a clock synchronised register for you.  this is how you construct pipelines.