[libre-riscv-dev] Fwd: [Mesa-dev] [XDC 2020] Virtual conference + Call for Proposals...
[libre-riscv-dev.git] / 43 / f7598a8a37761f98f34d22f7e1536681bd1a77
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17 From: Staf Verhaegen <staf@fibraservi.eu>
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65 Luke Kenneth Casson Leighton schreef op vr 27-03-2020 om 09:44 [+0000]:
66 > On Fri, Mar 27, 2020 at 9:25 AM Staf Verhaegen <staf@fibraservi.eu> wrote=
67 :
68 > > My point is that you will have the same performance for the fixed 5-sta=
69 ge pipeline running @ 800MHz
70 >=20
71 > no, it won't: it'll be half the clock speed. it won't be double thenumbe=
72 r of computations: it'll be the exact same number ofcomputations. therefor=
73 e, half the speed means half the number ofcomputations because the *through=
74 put* is the same
75 > when you use "cpufreq-set" to change the clock rate, if the clock rateis =
76 halved, the computer is twice as slow.
77
78 You are right.
79
80 > yes it's confusing :)
81
82 Yes and no, it is the basic functionality of a pipeline :(
83 You have the same latency but can have double the number of operations in f=
84 light.
85
86 greets,
87 Staf.
88
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