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  17 From: Staf Verhaegen <staf@fibraservi.eu>
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  19 Date: Fri, 27 Mar 2020 10:40:50 +0100
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  36 Subject: Re: [libre-riscv-dev] cache SRAM organisation
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  64
  65 Luke Kenneth Casson Leighton schreef op vr 27-03-2020 om 09:16 [+0000]:
  66 > On Fri, Mar 27, 2020 at 9:09 AM Staf Verhaegen <staf@fibraservi.eu> wrote=
  67 :
  68 > > I still feel you intermix synchronous and write-through in this stateme=
  69 nt, the above seems to be possible with synchronous SRAMs.
  70 >=20
  71 > this would be good.  what would help clarify immensely is if you couldlet=
  72  us know what options to nmigen Memory class are "supported".then it is rea=
  73 lly clear.
  74
  75 The nmigen Memory abstraction does not seem to allow a good representation =
  76 of a write-through SRAM. AFAICS it does not allow to have the output of the=
  77  read port be changed by what you write on the write port.
  78
  79 greets,
  80 Staf.
  81
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