Re: [libre-riscv-dev] minimum viable ASIC
[libre-riscv-dev.git] / 5c / b0f8c05b11061b976080b7098d311857ac4e23
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17 From: Staf Verhaegen <staf@fibraservi.eu>
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57 Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 11:42 [+0100]:
58 > On Friday, May 8, 2020, Staf Verhaegen <staf@fibraservi.eu> wrote:
59 > > Why only 24MHz without PLL ? You should have problems getting externalc=
60 lock frequencies up to 100MHz without a problem inside a chip.
61 >=20
62 > really? great! and that's driven from an external 100mhz clock? it seem=
63 sa little high, i guess i am used to SoCs which all run from a 24mhz XTAL.
64
65 There exist clock generator chips, some of them even programmable over a se=
66 rial bus interface. In the retro world amiga 75MHz accelerator cards or abo=
67 ve are not unheard of.
68 greets,Staf.
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