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  31 References: <CAPweEDw862-S1=Au1YbsKNy0629pa56eShp+2o_Avd96Auz8mw@mail.gmail.com>
  32  <9191058ea0912f2b508a6f73ea567e5f@f-cpu.org>
  33  <CAPweEDzdkhVJuJ3_UqZTbd7i7vXJ5iiu3qz+LUBsFRJrzCcEmQ@mail.gmail.com>
  34  <63e8b9ce54648590e2a6fc51bc2110dde7585f5e.camel@fibraservi.eu>
  35  <CAPweEDx5zV3K3y=gjpArhpZ5VrKYL01=938EYA4xd0PjROqppg@mail.gmail.com>
  36  <803285a5aa4bed5be9c8d4bc5855f49174742f33.camel@fibraservi.eu>
  37 In-Reply-To: <803285a5aa4bed5be9c8d4bc5855f49174742f33.camel@fibraservi.eu>
  38 From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  39 Date: Wed, 20 May 2020 18:22:11 +0100
  40 X-Gmail-Original-Message-ID: <CAPweEDxRMyVdga44mJ6GL+jOHxAz=DrwqFJEB013Eh3rVqCb6A@mail.gmail.com>
  41 Message-ID: <CAPweEDxRMyVdga44mJ6GL+jOHxAz=DrwqFJEB013Eh3rVqCb6A@mail.gmail.com>
  42 To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
  43 Subject: Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
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