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  17 From: Staf Verhaegen <staf@fibraservi.eu>
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  19 Date: Thu, 26 Mar 2020 13:31:38 +0100
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  31 Subject: Re: [libre-riscv-dev] cache SRAM organisation
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  47 Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org
  48 Sender: "libre-riscv-dev" <libre-riscv-dev-bounces@lists.libre-riscv.org>
  49
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  59
  60 (Sorry send to early)
  61
  62
  63 > .In theory on a single port SRAM
  64
  65 In theory on a single port SRAM the write data input and the Q data output =
  66 could be on opposite sides of the block but I will make sure that these pin=
  67 s are on the same side of the block and close together so you don't need mu=
  68 ch wire to connect a pass-through MUX.
  69
  70 greets,
  71 Staf.
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