ca0f40e1ecadc29726ea2e5085a40ee26722ab07
1 # Copyright (c) 2012 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2005-2008 The Regents of The University of Michigan
14 # All rights reserved.
16 # Redistribution and use in source and binary forms, with or without
17 # modification, are permitted provided that the following conditions are
18 # met: redistributions of source code must retain the above copyright
19 # notice, this list of conditions and the following disclaimer;
20 # redistributions in binary form must reproduce the above copyright
21 # notice, this list of conditions and the following disclaimer in the
22 # documentation and/or other materials provided with the distribution;
23 # neither the name of the copyright holders nor the names of its
24 # contributors may be used to endorse or promote products derived from
25 # this software without specific prior written permission.
27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 # Authors: Nathan Binkert
42 from MemObject
import MemObject
43 from System
import System
44 from m5
.params
import *
45 from m5
.proxy
import *
47 class BaseBus(MemObject
):
50 cxx_header
= "mem/bus.hh"
51 slave
= VectorSlavePort("vector port for connecting masters")
52 master
= VectorMasterPort("vector port for connecting slaves")
53 header_cycles
= Param
.Cycles(1, "cycles of overhead per transaction")
54 width
= Param
.Unsigned(8, "bus width (bytes)")
55 block_size
= Param
.Unsigned(64, "The default block size if not set by " \
56 "any connected module")
58 # The default port can be left unconnected, or be used to connect
59 # a default slave port
60 default
= MasterPort("Port for connecting an optional default slave")
62 # The default port can be used unconditionally, or based on
63 # address range, in which case it may overlap with other
64 # ports. The default range is always checked first, thus creating
65 # a two-level hierarchical lookup. This is useful e.g. for the PCI
67 use_default_range
= Param
.Bool(False, "Perform address mapping for " \
70 class NoncoherentBus(BaseBus
):
71 type = 'NoncoherentBus'
72 cxx_header
= "mem/noncoherent_bus.hh"
74 class CoherentBus(BaseBus
):
76 cxx_header
= "mem/coherent_bus.hh"
78 system
= Param
.System(Parent
.any
, "System that the bus belongs to.")