Add "autoname" pass and use it in "synth_ice40"
[yosys.git] / CHANGELOG
1
2 List of major changes and improvements between releases
3 =======================================================
4
5
6 Yosys 0.9 .. Yosys 0.9-dev
7 --------------------------
8
9 * Various
10 - Added "write_xaiger" backend
11 - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
12 - Added "synth_xilinx -abc9" (experimental)
13 - Added "synth_ice40 -abc9" (experimental)
14 - Added "synth -abc9" (experimental)
15 - Added "script -scriptwire"
16 - Added "synth_xilinx -nocarry"
17 - Added "synth_xilinx -nowidelut"
18 - Added "synth_ecp5 -nowidelut"
19 - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
20 - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
21 - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
22 - Renamed labels in synth_intel (e.g. bram -> map_bram)
23 - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
24 - Added automatic gzip decompression for frontends
25 - Added $_NMUX_ cell type
26 - Added automatic gzip compression (based on filename extension) for backends
27 - Improve attribute and parameter encoding in JSON to avoid ambiguities between
28 bit vectors and strings containing [01xz]*
29 - Added "clkbufmap" pass
30 - Added "extractinv" pass and "invertible_pin" attribute
31 - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
32 - Added "synth_xilinx -ise" (experimental)
33 - Added "synth_xilinx -iopad"
34 - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
35 - Improvements in pmgen: subpattern and recursive matches
36 - Added "opt_share" pass, run as part of "opt -full"
37 - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
38 - Removed "ice40_unlut"
39 - Improvements in pmgen: slices, choices, define, generate
40 - Added "xilinx_srl" for Xilinx shift register extraction
41 - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
42 - Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
43 - Added "-match-init" option to "dff2dffs" pass
44 - Added "techmap_autopurge" support to techmap
45 - Added "add -mod <modname[s]>"
46 - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
47 - Added "ice40_dsp" for Lattice iCE40 DSP packing
48 - Added "xilinx_dsp" for Xilinx DSP packing
49 - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
50 - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
51 - "synth_ice40 -dsp" to infer DSP blocks
52 - Added latch support to synth_xilinx
53 - Added "check -mapped"
54
55 Yosys 0.8 .. Yosys 0.9
56 ----------------------
57
58 * Various
59 - Many bugfixes and small improvements
60 - Added support for SystemVerilog interfaces and modports
61 - Added "write_edif -attrprop"
62 - Added "opt_lut" pass
63 - Added "gate2lut.v" techmap rule
64 - Added "rename -src"
65 - Added "equiv_opt" pass
66 - Added "flowmap" LUT mapping pass
67 - Added "rename -wire" to rename cells based on the wires they drive
68 - Added "bugpoint" for creating minimised testcases
69 - Added "write_edif -gndvccy"
70 - "write_verilog" to escape Verilog keywords
71 - Fixed sign handling of real constants
72 - "write_verilog" to write initial statement for initial flop state
73 - Added pmgen pattern matcher generator
74 - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
75 - Added "setundef -params" to replace undefined cell parameters
76 - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
77 - Fixed handling of defparam when default_nettype is none
78 - Fixed "wreduce" flipflop handling
79 - Fixed FIRRTL to Verilog process instance subfield assignment
80 - Added "write_verilog -siminit"
81 - Several fixes and improvements for mem2reg memories
82 - Fixed handling of task output ports in clocked always blocks
83 - Improved handling of and-with-1 and or-with-0 in "opt_expr"
84 - Added "read_aiger" frontend
85 - Added "mutate" pass
86 - Added "hdlname" attribute
87 - Added "rename -output"
88 - Added "read_ilang -lib"
89 - Improved "proc" full_case detection and handling
90 - Added "whitebox" and "lib_whitebox" attributes
91 - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
92 - Added Python bindings and support for Python plug-ins
93 - Added "pmux2shiftx"
94 - Added log_debug framework for reduced default verbosity
95 - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
96 - Added "peepopt" peephole optimisation pass using pmgen
97 - Added approximate support for SystemVerilog "var" keyword
98 - Added parsing of "specify" blocks into $specrule and $specify[23]
99 - Added support for attributes on parameters and localparams
100 - Added support for parsing attributes on port connections
101 - Added "wreduce -keepdc"
102 - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
103 - Added Verilog wand/wor wire type support
104 - Added support for elaboration system tasks
105 - Added "muxcover -mux{4,8,16}=<cost>"
106 - Added "muxcover -dmux=<cost>"
107 - Added "muxcover -nopartial"
108 - Added "muxpack" pass
109 - Added "pmux2shiftx -norange"
110 - Added support for "~" in filename parsing
111 - Added "read_verilog -pwires" feature to turn parameters into wires
112 - Fixed sign extension of unsized constants with 'bx and 'bz MSB
113 - Fixed genvar to be a signed type
114 - Added support for attributes on case rules
115 - Added "upto" and "offset" to JSON frontend and backend
116 - Several liberty file parser improvements
117 - Fixed handling of more complex BRAM patterns
118 - Add "write_aiger -I -O -B"
119
120 * Formal Verification
121 - Added $changed support to read_verilog
122 - Added "read_verilog -noassert -noassume -assert-assumes"
123 - Added btor ops for $mul, $div, $mod and $concat
124 - Added yosys-smtbmc support for btor witnesses
125 - Added "supercover" pass
126 - Fixed $global_clock handling vs autowire
127 - Added $dffsr support to "async2sync"
128 - Added "fmcombine" pass
129 - Added memory init support in "write_btor"
130 - Added "cutpoint" pass
131 - Changed "ne" to "neq" in btor2 output
132 - Added support for SVA "final" keyword
133 - Added "fmcombine -initeq -anyeq"
134 - Added timescale and generated-by header to yosys-smtbmc vcd output
135 - Improved BTOR2 handling of undriven wires
136
137 * Verific support
138 - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
139 - Improved support for asymmetric memories
140 - Added "verific -chparam"
141 - Fixed "verific -extnets" for more complex situations
142 - Added "read -verific" and "read -noverific"
143 - Added "hierarchy -chparam"
144
145 * New back-ends
146 - Added initial Anlogic support
147 - Added initial SmartFusion2 and IGLOO2 support
148
149 * ECP5 support
150 - Added "synth_ecp5 -nowidelut"
151 - Added BRAM inference support to "synth_ecp5"
152 - Added support for transforming Diamond IO and flipflop primitives
153
154 * iCE40 support
155 - Added "ice40_unlut" pass
156 - Added "synth_ice40 -relut"
157 - Added "synth_ice40 -noabc"
158 - Added "synth_ice40 -dffe_min_ce_use"
159 - Added DSP inference support using pmgen
160 - Added support for initialising BRAM primitives from a file
161 - Added iCE40 Ultra RGB LED driver cells
162
163 * Xilinx support
164 - Use "write_edif -pvector bra" for Xilinx EDIF files
165 - Fixes for VPR place and route support with "synth_xilinx"
166 - Added more cell simulation models
167 - Added "synth_xilinx -family"
168 - Added "stat -tech xilinx" to estimate logic cell usage
169 - Added "synth_xilinx -nocarry"
170 - Added "synth_xilinx -nowidelut"
171 - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
172 - Added support for mapping RAM32X1D
173
174 Yosys 0.7 .. Yosys 0.8
175 ----------------------
176
177 * Various
178 - Many bugfixes and small improvements
179 - Strip debug symbols from installed binary
180 - Replace -ignore_redef with -[no]overwrite in front-ends
181 - Added write_verilog hex dump support, add -nohex option
182 - Added "write_verilog -decimal"
183 - Added "scc -set_attr"
184 - Added "verilog_defines" command
185 - Remember defines from one read_verilog to next
186 - Added support for hierarchical defparam
187 - Added FIRRTL back-end
188 - Improved ABC default scripts
189 - Added "design -reset-vlog"
190 - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
191 - Added Verilog $rtoi and $itor support
192 - Added "check -initdrv"
193 - Added "read_blif -wideports"
194 - Added support for SystemVerilog "++" and "--" operators
195 - Added support for SystemVerilog unique, unique0, and priority case
196 - Added "write_edif" options for edif "flavors"
197 - Added support for resetall compiler directive
198 - Added simple C beck-end (bitwise combinatorical only atm)
199 - Added $_ANDNOT_ and $_ORNOT_ cell types
200 - Added cell library aliases to "abc -g"
201 - Added "setundef -anyseq"
202 - Added "chtype" command
203 - Added "design -import"
204 - Added "write_table" command
205 - Added "read_json" command
206 - Added "sim" command
207 - Added "extract_fa" and "extract_reduce" commands
208 - Added "extract_counter" command
209 - Added "opt_demorgan" command
210 - Added support for $size and $bits SystemVerilog functions
211 - Added "blackbox" command
212 - Added "ltp" command
213 - Added support for editline as replacement for readline
214 - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
215 - Added "yosys -E" for creating Makefile dependencies files
216 - Added "synth -noshare"
217 - Added "memory_nordff"
218 - Added "setundef -undef -expose -anyconst"
219 - Added "expose -input"
220 - Added specify/specparam parser support (simply ignore them)
221 - Added "write_blif -inames -iattr"
222 - Added "hierarchy -simcheck"
223 - Added an option to statically link abc into yosys
224 - Added protobuf back-end
225 - Added BLIF parsing support for .conn and .cname
226 - Added read_verilog error checking for reg/wire/logic misuse
227 - Added "make coverage" and ENABLE_GCOV build option
228
229 * Changes in Yosys APIs
230 - Added ConstEval defaultval feature
231 - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
232 - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
233 - Added log_file_warning() and log_file_error() functions
234
235 * Formal Verification
236 - Added "write_aiger"
237 - Added "yosys-smtbmc --aig"
238 - Added "always <positive_int>" to .smtc format
239 - Added $cover cell type and support for cover properties
240 - Added $fair/$live cell type and support for liveness properties
241 - Added smtbmc support for memory vcd dumping
242 - Added "chformal" command
243 - Added "write_smt2 -stbv" and "write_smt2 -stdt"
244 - Fix equiv_simple, old behavior now available with "equiv_simple -short"
245 - Change to Yices2 as default SMT solver (it is GPL now)
246 - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
247 - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
248 - Added a brand new "write_btor" command for BTOR2
249 - Added clk2fflogic memory support and other improvements
250 - Added "async memory write" support to write_smt2
251 - Simulate clock toggling in yosys-smtbmc VCD output
252 - Added $allseq/$allconst cells for EA-solving
253 - Make -nordff the default in "prep"
254 - Added (* gclk *) attribute
255 - Added "async2sync" pass for single-clock designs with async resets
256
257 * Verific support
258 - Many improvements in Verific front-end
259 - Added proper handling of concurent SVA properties
260 - Map "const" and "rand const" to $anyseq/$anyconst
261 - Added "verific -import -flatten" and "verific -import -extnets"
262 - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
263 - Remove PSL support (because PSL has been removed in upstream Verific)
264 - Improve integration with "hierarchy" command design elaboration
265 - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
266 - Added simpilied "read" command that automatically uses verific if available
267 - Added "verific -set-<severity> <msg_id>.."
268 - Added "verific -work <libname>"
269
270 * New back-ends
271 - Added initial Coolrunner-II support
272 - Added initial eASIC support
273 - Added initial ECP5 support
274
275 * GreenPAK Support
276 - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
277
278 * iCE40 Support
279 - Add "synth_ice40 -vpr"
280 - Add "synth_ice40 -nodffe"
281 - Add "synth_ice40 -json"
282 - Add Support for UltraPlus cells
283
284 * MAX10 and Cyclone IV Support
285 - Added initial version of metacommand "synth_intel".
286 - Improved write_verilog command to produce VQM netlist for Quartus Prime.
287 - Added support for MAX10 FPGA family synthesis.
288 - Added support for Cyclone IV family synthesis.
289 - Added example of implementation for DE2i-150 board.
290 - Added example of implementation for MAX10 development kit.
291 - Added LFSR example from Asic World.
292 - Added "dffinit -highlow" for mapping to Intel primitives
293
294
295 Yosys 0.6 .. Yosys 0.7
296 ----------------------
297
298 * Various
299 - Added "yosys -D" feature
300 - Added support for installed plugins in $(DATDIR)/plugins/
301 - Renamed opt_const to opt_expr
302 - Renamed opt_share to opt_merge
303 - Added "prep -flatten" and "synth -flatten"
304 - Added "prep -auto-top" and "synth -auto-top"
305 - Using "mfs" and "lutpack" in ABC lut mapping
306 - Support for abstract modules in chparam
307 - Cleanup abstract modules at end of "hierarchy -top"
308 - Added tristate buffer support to iopadmap
309 - Added opt_expr support for div/mod by power-of-two
310 - Added "select -assert-min <N> -assert-max <N>"
311 - Added "attrmvcp" pass
312 - Added "attrmap" command
313 - Added "tee +INT -INT"
314 - Added "zinit" pass
315 - Added "setparam -type"
316 - Added "shregmap" pass
317 - Added "setundef -init"
318 - Added "nlutmap -assert"
319 - Added $sop cell type and "abc -sop -I <num> -P <num>"
320 - Added "dc2" to default ABC scripts
321 - Added "deminout"
322 - Added "insbuf" command
323 - Added "prep -nomem"
324 - Added "opt_rmdff -keepdc"
325 - Added "prep -nokeepdc"
326 - Added initial version of "synth_gowin"
327 - Added "fsm_expand -full"
328 - Added support for fsm_encoding="user"
329 - Many improvements in GreenPAK4 support
330 - Added black box modules for all Xilinx 7-series lib cells
331 - Added synth_ice40 support for latches via logic loops
332 - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
333
334 * Build System
335 - Added ABCEXTERNAL and ABCURL make variables
336 - Added BINDIR, LIBDIR, and DATDIR make variables
337 - Added PKG_CONFIG make variable
338 - Added SEED make variable (for "make test")
339 - Added YOSYS_VER_STR make variable
340 - Updated min GCC requirement to GCC 4.8
341 - Updated required Bison version to Bison 3.x
342
343 * Internal APIs
344 - Added ast.h to exported headers
345 - Added ScriptPass helper class for script-like passes
346 - Added CellEdgesDatabase API
347
348 * Front-ends and Back-ends
349 - Added filename glob support to all front-ends
350 - Added avail (black-box) module params to ilang format
351 - Added $display %m support
352 - Added support for $stop Verilog system task
353 - Added support for SystemVerilog packages
354 - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
355 - Added support for "active high" and "active low" latches in read_blif and write_blif
356 - Use init value "2" for all uninitialized FFs in BLIF back-end
357 - Added "read_blif -sop"
358 - Added "write_blif -noalias"
359 - Added various write_blif options for VTR support
360 - write_json: also write module attributes.
361 - Added "write_verilog -nodec -nostr -defparam"
362 - Added "read_verilog -norestrict -assume-asserts"
363 - Added support for bus interfaces to "read_liberty -lib"
364 - Added liberty parser support for types within cell decls
365 - Added "write_verilog -renameprefix -v"
366 - Added "write_edif -nogndvcc"
367
368 * Formal Verification
369 - Support for hierarchical designs in smt2 back-end
370 - Yosys-smtbmc: Support for hierarchical VCD dumping
371 - Added $initstate cell type and vlog function
372 - Added $anyconst and $anyseq cell types and vlog functions
373 - Added printing of code loc of failed asserts to yosys-smtbmc
374 - Added memory_memx pass, "memory -memx", and "prep -memx"
375 - Added "proc_mux -ifx"
376 - Added "yosys-smtbmc -g"
377 - Deprecated "write_smt2 -regs" (by default on now)
378 - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
379 - Added support for memories to smtio.py
380 - Added "yosys-smtbmc --dump-vlogtb"
381 - Added "yosys-smtbmc --smtc --dump-smtc"
382 - Added "yosys-smtbmc --dump-all"
383 - Added assertpmux command
384 - Added "yosys-smtbmc --unroll"
385 - Added $past, $stable, $rose, $fell SVA functions
386 - Added "yosys-smtbmc --noinfo and --dummy"
387 - Added "yosys-smtbmc --noincr"
388 - Added "yosys-smtbmc --cex <filename>"
389 - Added $ff and $_FF_ cell types
390 - Added $global_clock verilog syntax support for creating $ff cells
391 - Added clk2fflogic
392
393
394 Yosys 0.5 .. Yosys 0.6
395 ----------------------
396
397 * Various
398 - Added Contributor Covenant Code of Conduct
399 - Various improvements in dict<> and pool<>
400 - Added hashlib::mfp and refactored SigMap
401 - Improved support for reals as module parameters
402 - Various improvements in SMT2 back-end
403 - Added "keep_hierarchy" attribute
404 - Verilog front-end: define `BLACKBOX in -lib mode
405 - Added API for converting internal cells to AIGs
406 - Added ENABLE_LIBYOSYS Makefile option
407 - Removed "techmap -share_map" (use "-map +/filename" instead)
408 - Switched all Python scripts to Python 3
409 - Added support for $display()/$write() and $finish() to Verilog front-end
410 - Added "yosys-smtbmc" formal verification flow
411 - Added options for clang sanitizers to Makefile
412
413 * New commands and options
414 - Added "scc -expect <N> -nofeedback"
415 - Added "proc_dlatch"
416 - Added "check"
417 - Added "select %xe %cie %coe %M %C %R"
418 - Added "sat -dump_json" (WaveJSON format)
419 - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
420 - Added "sat -stepsize" and "sat -tempinduct-step"
421 - Added "sat -show-regs -show-public -show-all"
422 - Added "write_json" (Native Yosys JSON format)
423 - Added "write_blif -attr"
424 - Added "dffinit"
425 - Added "chparam"
426 - Added "muxcover"
427 - Added "pmuxtree"
428 - Added memory_bram "make_outreg" feature
429 - Added "splice -wires"
430 - Added "dff2dffe -direct-match"
431 - Added simplemap $lut support
432 - Added "read_blif"
433 - Added "opt_share -share_all"
434 - Added "aigmap"
435 - Added "write_smt2 -mem -regs -wires"
436 - Added "memory -nordff"
437 - Added "write_smv"
438 - Added "synth -nordff -noalumacc"
439 - Added "rename -top new_name"
440 - Added "opt_const -clkinv"
441 - Added "synth -nofsm"
442 - Added "miter -assert"
443 - Added "read_verilog -noautowire"
444 - Added "read_verilog -nodpi"
445 - Added "tribuf"
446 - Added "lut2mux"
447 - Added "nlutmap"
448 - Added "qwp"
449 - Added "test_cell -noeval"
450 - Added "edgetypes"
451 - Added "equiv_struct"
452 - Added "equiv_purge"
453 - Added "equiv_mark"
454 - Added "equiv_add -try -cell"
455 - Added "singleton"
456 - Added "abc -g -luts"
457 - Added "torder"
458 - Added "write_blif -cname"
459 - Added "submod -copy"
460 - Added "dffsr2dff"
461 - Added "stat -liberty"
462
463 * Synthesis metacommands
464 - Various improvements in synth_xilinx
465 - Added synth_ice40 and synth_greenpak4
466 - Added "prep" metacommand for "synthesis lite"
467
468 * Cell library changes
469 - Added cell types to "help" system
470 - Added $meminit cell type
471 - Added $assume cell type
472 - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
473 - Added $tribuf and $_TBUF_ cell types
474 - Added read-enable to memory model
475
476 * YosysJS
477 - Various improvements in emscripten build
478 - Added alternative webworker-based JS API
479 - Added a few example applications
480
481
482 Yosys 0.4 .. Yosys 0.5
483 ----------------------
484
485 * API changes
486 - Added log_warning()
487 - Added eval_select_args() and eval_select_op()
488 - Added cell->known(), cell->input(portname), cell->output(portname)
489 - Skip blackbox modules in design->selected_modules()
490 - Replaced std::map<> and std::set<> with dict<> and pool<>
491 - New SigSpec::extend() is what used to be SigSpec::extend_u0()
492 - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
493
494 * Cell library changes
495 - Added flip-flops with enable ($dffe etc.)
496 - Added $equiv cells for equivalence checking framework
497
498 * Various
499 - Updated ABC to hg rev 61ad5f908c03
500 - Added clock domain partitioning to ABC pass
501 - Improved plugin building (see "yosys-config --build")
502 - Added ENABLE_NDEBUG Makefile flag for high-performance builds
503 - Added "yosys -d", "yosys -L" and other driver improvements
504 - Added support for multi-bit (array) cell ports to "write_edif"
505 - Now printing most output to stdout, not stderr
506 - Added "onehot" attribute (set by "fsm_map")
507 - Various performance improvements
508 - Vastly improved Xilinx flow
509 - Added "make unsintall"
510
511 * Equivalence checking
512 - Added equivalence checking commands:
513 equiv_make equiv_simple equiv_status
514 equiv_induct equiv_miter
515 equiv_add equiv_remove
516
517 * Block RAM support:
518 - Added "memory_bram" command
519 - Added BRAM support to Xilinx flow
520
521 * Other New Commands and Options
522 - Added "dff2dffe"
523 - Added "fsm -encfile"
524 - Added "dfflibmap -prepare"
525 - Added "write_blid -unbuf -undef -blackbox"
526 - Added "write_smt2" for writing SMT-LIBv2 files
527 - Added "test_cell -w -muxdiv"
528 - Added "select -read"
529
530
531 Yosys 0.3.0 .. Yosys 0.4
532 ------------------------
533
534 * Platform Support
535 - Added support for mxe-based cross-builds for win32
536 - Added sourcecode-export as VisualStudio project
537 - Added experimental EMCC (JavaScript) support
538
539 * Verilog Frontend
540 - Added -sv option for SystemVerilog (and automatic *.sv file support)
541 - Added support for real-valued constants and constant expressions
542 - Added support for non-standard "via_celltype" attribute on task/func
543 - Added support for non-standard "module mod_name(...);" syntax
544 - Added support for non-standard """ macro bodies
545 - Added support for array with more than one dimension
546 - Added support for $readmemh and $readmemb
547 - Added support for DPI functions
548
549 * Changes in internal cell library
550 - Added $shift and $shiftx cell types
551 - Added $alu, $lcu, $fa and $macc cell types
552 - Removed $bu0 and $safe_pmux cell types
553 - $mem/$memwr WR_EN input is now a per-data-bit enable signal
554 - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
555 - Renamed ports of $lut cells (from I->O to A->Y)
556 - Renamed $_INV_ to $_NOT_
557
558 * Changes for simple synthesis flows
559 - There is now a "synth" command with a recommended default script
560 - Many improvements in synthesis of arithmetic functions to gates
561 - Multipliers and adders with many operands are using carry-save adder trees
562 - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
563 - Various new high-level optimizations on RTL netlist
564 - Various improvements in FSM optimization
565 - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
566
567 * Changes in internal APIs and RTLIL
568 - Added log_id() and log_cell() helper functions
569 - Added function-like cell creation helpers
570 - Added GetSize() function (like .size() but with int)
571 - Major refactoring of RTLIL::Module and related classes
572 - Major refactoring of RTLIL::SigSpec and related classes
573 - Now RTLIL::IdString is essentially an int
574 - Added macros for code coverage counters
575 - Added some Makefile magic for pretty make logs
576 - Added "kernel/yosys.h" with all the core definitions
577 - Changed a lot of code from FILE* to c++ streams
578 - Added RTLIL::Monitor API and "trace" command
579 - Added "Yosys" C++ namespace
580
581 * Changes relevant to SAT solving
582 - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
583 - Added native ezSAT support for vector shift ops
584 - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
585
586 * New commands (or large improvements to commands)
587 - Added "synth" command with default script
588 - Added "share" (finally some real resource sharing)
589 - Added "memory_share" (reduce number of ports on memories)
590 - Added "wreduce" and "alumacc" commands
591 - Added "opt -keepdc -fine -full -fast"
592 - Added some "test_*" commands
593
594 * Various other changes
595 - Added %D and %c select operators
596 - Added support for labels in yosys scripts
597 - Added support for here-documents in yosys scripts
598 - Support "+/" prefix for files from proc_share_dir
599 - Added "autoidx" statement to ilang language
600 - Switched from "yosys-svgviewer" to "xdot"
601 - Renamed "stdcells.v" to "techmap.v"
602 - Various bug fixes and small improvements
603 - Improved welcome and bye messages
604
605
606 Yosys 0.2.0 .. Yosys 0.3.0
607 --------------------------
608
609 * Driver program and overall behavior:
610 - Added "design -push" and "design -pop"
611 - Added "tee" command for redirecting log output
612
613 * Changes in the internal cell library:
614 - Added $dlatchsr and $_DLATCHSR_???_ cell types
615
616 * Improvements in Verilog frontend:
617 - Improved support for const functions (case, always, repeat)
618 - The generate..endgenerate keywords are now optional
619 - Added support for arrays of module instances
620 - Added support for "`default_nettype" directive
621 - Added support for "`line" directive
622
623 * Other front- and back-ends:
624 - Various changes to "write_blif" options
625 - Various improvements in EDIF backend
626 - Added "vhdl2verilog" pseudo-front-end
627 - Added "verific" pseudo-front-end
628
629 * Improvements in technology mapping:
630 - Added support for recursive techmap
631 - Added CONSTMSK and CONSTVAL features to techmap
632 - Added _TECHMAP_CONNMAP_*_ feature to techmap
633 - Added _TECHMAP_REPLACE_ feature to techmap
634 - Added "connwrappers" command for wrap-extract-unwrap method
635 - Added "extract -map %<design_name>" feature
636 - Added "extract -ignore_param ..." and "extract -ignore_parameters"
637 - Added "techmap -max_iter" option
638
639 * Improvements to "eval" and "sat" framework:
640 - Now include a copy of Minisat (with build fixes applied)
641 - Switched to Minisat::SimpSolver as SAT back-end
642 - Added "sat -dump_vcd" feature
643 - Added "sat -dump_cnf" feature
644 - Added "sat -initsteps <N>" feature
645 - Added "freduce -stop <N>" feature
646 - Added "freduce -dump <prefix>" feature
647
648 * Integration with ABC:
649 - Updated ABC rev to 7600ffb9340c
650
651 * Improvements in the internal APIs:
652 - Added RTLIL::Module::add... helper methods
653 - Various build fixes for OSX (Darwin) and OpenBSD
654
655
656 Yosys 0.1.0 .. Yosys 0.2.0
657 --------------------------
658
659 * Changes to the driver program:
660 - Added "yosys -h" and "yosys -H"
661 - Added support for backslash line continuation in scripts
662 - Added support for #-comments in same line as command
663 - Added "echo" and "log" commands
664
665 * Improvements in Verilog frontend:
666 - Added support for local registers in named blocks
667 - Added support for "case" in "generate" blocks
668 - Added support for $clog2 system function
669 - Added support for basic SystemVerilog assert statements
670 - Added preprocessor support for macro arguments
671 - Added preprocessor support for `elsif statement
672 - Added "verilog_defaults" command
673 - Added read_verilog -icells option
674 - Added support for constant sizes from parameters
675 - Added "read_verilog -setattr"
676 - Added support for function returning 'integer'
677 - Added limited support for function calls in parameter values
678 - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
679
680 * Other front- and back-ends:
681 - Added BTOR backend
682 - Added Liberty frontend
683
684 * Improvements in technology mapping:
685 - The "dfflibmap" command now strongly prefers solutions with
686 no inverters in clock paths
687 - The "dfflibmap" command now prefers cells with smaller area
688 - Added support for multiple -map options to techmap
689 - Added "dfflibmap" support for //-comments in liberty files
690 - Added "memory_unpack" command to revert "memory_collect"
691 - Added standard techmap rule "techmap -share_map pmux2mux.v"
692 - Added "iopadmap -bits"
693 - Added "setundef" command
694 - Added "hilomap" command
695
696 * Changes in the internal cell library:
697 - Major rewrite of simlib.v for better compatibility with other tools
698 - Added PRIORITY parameter to $memwr cells
699 - Added TRANSPARENT parameter to $memrd cells
700 - Added RD_TRANSPARENT parameter to $mem cells
701 - Added $bu0 cell (always 0-extend, even undef MSB)
702 - Added $assert cell type
703 - Added $slice and $concat cell types
704
705 * Integration with ABC:
706 - Updated ABC to hg rev 2058c8ccea68
707 - Tighter integration of ABC build with Yosys build. The make
708 targets 'make abc' and 'make install-abc' are now obsolete.
709 - Added support for passing FFs from one clock domain through ABC
710 - Now always use BLIF as exchange format with ABC
711 - Added support for "abc -script +<command_sequence>"
712 - Improved standard ABC recipe
713 - Added support for "keep" attribute to abc command
714 - Added "abc -dff / -clk / -keepff" options
715
716 * Improvements to "eval" and "sat" framework:
717 - Added support for "0" and "~0" in right-hand side -set expressions
718 - Added "eval -set-undef" and "eval -table"
719 - Added "sat -set-init" and "sat -set-init-*" for sequential problems
720 - Added undef support to SAT solver, incl. various new "sat" options
721 - Added correct support for === and !== for "eval" and "sat"
722 - Added "sat -tempinduct" (default -seq is now non-induction sequential)
723 - Added "sat -prove-asserts"
724 - Complete rewrite of the 'freduce' command
725 - Added "miter" command
726 - Added "sat -show-inputs" and "sat -show-outputs"
727 - Added "sat -ignore_unknown_cells" (now produce an error by default)
728 - Added "sat -falsify"
729 - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
730 - Added "expose" command
731 - Added support for @<sel_name> to sat and eval signal expressions
732
733 * Changes in the 'make test' framework and auxiliary test tools:
734 - Added autotest.sh -p and -f options
735 - Replaced autotest.sh ISIM support with XSIM support
736 - Added test cases for SAT framework
737
738 * Added "abbreviated IDs":
739 - Now $<something>$foo can be abbreviated as $foo.
740 - Usually this last part is a unique id (from RTLIL::autoidx)
741 - This abbreviated IDs are now also used in "show" output
742
743 * Other changes to selection framework:
744 - Now */ is optional in */<mode>:<arg> expressions
745 - Added "select -assert-none" and "select -assert-any"
746 - Added support for matching modules by attribute (A:<expr>)
747 - Added "select -none"
748 - Added support for r:<expr> pattern for matching cell parameters
749 - Added support for !=, <, <=, >=, > for attribute and parameter matching
750 - Added support for %s for selecting sub-modules
751 - Added support for %m for expanding selections to whole modules
752 - Added support for i:*, o:* and x:* pattern for selecting module ports
753 - Added support for s:<expr> pattern for matching wire width
754 - Added support for %a operation to select wire aliases
755
756 * Various other changes to commands and options:
757 - The "ls" command now supports wildcards
758 - Added "show -pause" and "show -format dot"
759 - Added "show -color" support for cells
760 - Added "show -label" and "show -notitle"
761 - Added "dump -m" and "dump -n"
762 - Added "history" command
763 - Added "rename -hide"
764 - Added "connect" command
765 - Added "splitnets -driver"
766 - Added "opt_const -mux_undef"
767 - Added "opt_const -mux_bool"
768 - Added "opt_const -undriven"
769 - Added "opt -mux_undef -mux_bool -undriven -purge"
770 - Added "hierarchy -libdir"
771 - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
772 - Added "delete" command
773 - Added "dump -append"
774 - Added "setattr" and "setparam" commands
775 - Added "design -stash/-copy-from/-copy-to"
776 - Added "copy" command
777 - Added "splice" command
778