2 List of major changes and improvements between releases
3 =======================================================
11 - Added eval_select_args() and eval_select_op()
12 - Added cell->known(), cell->input(portname), cell->output(portname)
13 - Skip blackbox modules in design->selected_modules()
14 - Replaced std::map<> and std::set<> with dict<> and pool<>
15 - New SigSpec::extend() is what used to be SigSpec::extend_u0()
16 - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
18 * Cell library changes
19 - Added flip-flops with enable ($dffe etc.)
20 - Added $equiv cells for equivalence checking framework
23 - Updated ABC to hg rev 61ad5f908c03
24 - Added clock domain partitioning to ABC pass
25 - Improved plugin building (see "yosys-config --build")
26 - Added ENABLE_NDEBUG Makefile flag for high-performance builds
27 - Added "yosys -d", "yosys -L" and other driver improvements
28 - Added support for multi-bit (array) cell ports to "write_edif"
29 - Now printing most output to stdout, not stderr
30 - Added "onehot" attribute (set by "fsm_map")
31 - Various performance improvements
32 - Vastly improved Xilinx flow
33 - Added "make unsintall"
35 * Equivalence checking
36 - Added equivalence checking commands:
37 equiv_make equiv_simple equiv_status
38 equiv_induct equiv_miter
39 equiv_add equiv_remove
42 - Added "memory_bram" command
43 - Added BRAM support to Xilinx flow
45 * Other New Commands and Options
47 - Added "fsm -encfile"
48 - Added "dfflibmap -prepare"
49 - Added "write_blid -unbuf -undef -blackbox"
50 - Added "write_smt2" for writing SMT-LIBv2 files
51 - Added "test_cell -w -muxdiv"
52 - Added "select -read"
55 Yosys 0.3.0 .. Yosys 0.4
56 ------------------------
59 - Added support for mxe-based cross-builds for win32
60 - Added sourcecode-export as VisualStudio project
61 - Added experimental EMCC (JavaScript) support
64 - Added -sv option for SystemVerilog (and automatic *.sv file support)
65 - Added support for real-valued constants and constant expressions
66 - Added support for non-standard "via_celltype" attribute on task/func
67 - Added support for non-standard "module mod_name(...);" syntax
68 - Added support for non-standard """ macro bodies
69 - Added support for array with more than one dimension
70 - Added support for $readmemh and $readmemb
71 - Added support for DPI functions
73 * Changes in internal cell library
74 - Added $shift and $shiftx cell types
75 - Added $alu, $lcu, $fa and $macc cell types
76 - Removed $bu0 and $safe_pmux cell types
77 - $mem/$memwr WR_EN input is now a per-data-bit enable signal
78 - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
79 - Renamed ports of $lut cells (from I->O to A->Y)
80 - Renamed $_INV_ to $_NOT_
82 * Changes for simple synthesis flows
83 - There is now a "synth" command with a recommended default script
84 - Many improvements in synthesis of arithmetic functions to gates
85 - Multiplieres and adders with many operands are using carry-save adder trees
86 - Remaining adders are now implemented using Brent–Kung carry look-ahead adders
87 - Various new high-level optimizations on RTL netlist
88 - Various improvements in FSM optimization
89 - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
91 * Changes in internal APIs and RTLIL
92 - Added log_id() and log_cell() helper functions
93 - Added function-like cell creation helpers
94 - Added GetSize() function (like .size() but with int)
95 - Major refactoring of RTLIL::Module and related classes
96 - Major refactoring of RTLIL::SigSpec and related classes
97 - Now RTLIL::IdString is essentially an int
98 - Added macros for code coverage counters
99 - Added some Makefile magic for pretty make logs
100 - Added "kernel/yosys.h" with all the core definitions
101 - Chanded a lot of code from FILE* to c++ streams
102 - Added RTLIL::Monitor API and "trace" command
103 - Added "Yosys" C++ namespace
105 * Changes relevant to SAT solving
106 - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
107 - Added native ezSAT support for vector shift ops
108 - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
110 * New commands (or large improvements to commands)
111 - Added "synth" command with default script
112 - Added "share" (finally some real resource sharing)
113 - Added "memory_share" (reduce number of ports on memories)
114 - Added "wreduce" and "alumacc" commands
115 - Added "opt -keepdc -fine -full -fast"
116 - Added some "test_*" commands
118 * Various other changes
119 - Added %D and %c select operators
120 - Added support for labels in yosys scripts
121 - Added support for here-documents in yosys scripts
122 - Support "+/" prefix for files from proc_share_dir
123 - Added "autoidx" statement to ilang language
124 - Switched from "yosys-svgviewer" to "xdot"
125 - Renamed "stdcells.v" to "techmap.v"
126 - Various bug fixes and small improvements
127 - Improved welcome and bye messages
130 Yosys 0.2.0 .. Yosys 0.3.0
131 --------------------------
133 * Driver program and overall behavior:
134 - Added "design -push" and "design -pop"
135 - Added "tee" command for redirecting log output
137 * Changes in the internal cell library:
138 - Added $dlatchsr and $_DLATCHSR_???_ cell types
140 * Improvements in Verilog frontend:
141 - Improved support for const functions (case, always, repeat)
142 - The generate..endgenerate keywords are now optional
143 - Added support for arrays of module instances
144 - Added support for "`default_nettype" directive
145 - Added support for "`line" directive
147 * Other front- and back-ends:
148 - Various changes to "write_blif" options
149 - Various improvements in EDIF backend
150 - Added "vhdl2verilog" pseudo-front-end
151 - Added "verific" pseudo-front-end
153 * Improvements in technology mapping:
154 - Added support for recursive techmap
155 - Added CONSTMSK and CONSTVAL features to techmap
156 - Added _TECHMAP_CONNMAP_*_ feature to techmap
157 - Added _TECHMAP_REPLACE_ feature to techmap
158 - Added "connwrappers" command for wrap-extract-unwrap method
159 - Added "extract -map %<design_name>" feature
160 - Added "extract -ignore_param ..." and "extract -ignore_parameters"
161 - Added "techmap -max_iter" option
163 * Improvements to "eval" and "sat" framework:
164 - Now include a copy of Minisat (with build fixes applied)
165 - Switched to Minisat::SimpSolver as SAT back-end
166 - Added "sat -dump_vcd" feature
167 - Added "sat -dump_cnf" feature
168 - Added "sat -initsteps <N>" feature
169 - Added "freduce -stop <N>" feature
170 - Added "fredure -dump <prefix>" feature
172 * Integration with ABC:
173 - Updated ABC rev to 7600ffb9340c
175 * Improvements in the internal APIs:
176 - Added RTLIL::Module::add... helper methods
177 - Various build fixes for OSX (Darwin) and OpenBSD
180 Yosys 0.1.0 .. Yosys 0.2.0
181 --------------------------
183 * Changes to the driver program:
184 - Added "yosys -h" and "yosys -H"
185 - Added support for backslash line continuation in scripts
186 - Added support for #-comments in same line as command
187 - Added "echo" and "log" commands
189 * Improvements in Verilog frontend:
190 - Added support for local registers in named blocks
191 - Added support for "case" in "generate" blocks
192 - Added support for $clog2 system function
193 - Added support for basic SystemVerilog assert statements
194 - Added preprocessor support for macro arguments
195 - Added preprocessor support for `elsif statement
196 - Added "verilog_defaults" command
197 - Added read_verilog -icells option
198 - Added support for constant sizes from parameters
199 - Added "read_verilog -setattr"
200 - Added support for function returning 'integer'
201 - Added limited support for function calls in parameter values
202 - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
204 * Other front- and back-ends:
206 - Added Liberty frontend
208 * Improvements in technology mapping:
209 - The "dfflibmap" command now strongly prefers solutions with
210 no inverters in clock paths
211 - The "dfflibmap" command now prefers cells with smaller area
212 - Added support for multiple -map options to techmap
213 - Added "dfflibmap" support for //-comments in liberty files
214 - Added "memory_unpack" command to revert "memory_collect"
215 - Added standard techmap rule "techmap -share_map pmux2mux.v"
216 - Added "iopadmap -bits"
217 - Added "setundef" command
218 - Added "hilomap" command
220 * Changes in the internal cell library:
221 - Major rewrite of simlib.v for better compatibility with other tools
222 - Added PRIORITY parameter to $memwr cells
223 - Added TRANSPARENT parameter to $memrd cells
224 - Added RD_TRANSPARENT parameter to $mem cells
225 - Added $bu0 cell (always 0-extend, even undef MSB)
226 - Added $assert cell type
227 - Added $slice and $concat cell types
229 * Integration with ABC:
230 - Updated ABC to hg rev 2058c8ccea68
231 - Tighter integration of ABC build with Yosys build. The make
232 targets 'make abc' and 'make install-abc' are now obsolete.
233 - Added support for passing FFs from one clock domain through ABC
234 - Now always use BLIF as exchange format with ABC
235 - Added support for "abc -script +<command_sequence>"
236 - Improved standard ABC recipe
237 - Added support for "keep" attribute to abc command
238 - Added "abc -dff / -clk / -keepff" options
240 * Improvements to "eval" and "sat" framework:
241 - Added support for "0" and "~0" in right-hand side -set expressions
242 - Added "eval -set-undef" and "eval -table"
243 - Added "sat -set-init" and "sat -set-init-*" for sequential problems
244 - Added undef support to SAT solver, incl. various new "sat" options
245 - Added correct support for === and !== for "eval" and "sat"
246 - Added "sat -tempinduct" (default -seq is now non-induction sequential)
247 - Added "sat -prove-asserts"
248 - Complete rewrite of the 'freduce' command
249 - Added "miter" command
250 - Added "sat -show-inputs" and "sat -show-outputs"
251 - Added "sat -ignore_unknown_cells" (now produce an error by default)
252 - Added "sat -falsify"
253 - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
254 - Added "expose" command
255 - Added support for @<sel_name> to sat and eval signal expressions
257 * Changes in the 'make test' framework and auxilary test tools:
258 - Added autotest.sh -p and -f options
259 - Replaced autotest.sh ISIM support with XSIM support
260 - Added test cases for SAT framework
262 * Added "abbreviated IDs":
263 - Now $<something>$foo can be abbriviated as $foo.
264 - Usually this last part is a unique id (from RTLIL::autoidx)
265 - This abbreviated IDs are now also used in "show" output
267 * Other changes to selection framework:
268 - Now */ is optional in */<mode>:<arg> expressions
269 - Added "select -assert-none" and "select -assert-any"
270 - Added support for matching modules by attribute (A:<expr>)
271 - Added "select -none"
272 - Added support for r:<expr> pattern for matching cell parameters
273 - Added support for !=, <, <=, >=, > for attribute and parameter matching
274 - Added support for %s for selecting sub-modules
275 - Added support for %m for expanding selections to whole modules
276 - Added support for i:*, o:* and x:* pattern for selecting module ports
277 - Added support for s:<expr> pattern for matching wire width
278 - Added support for %a operation to select wire aliases
280 * Various other changes to commands and options:
281 - The "ls" command now supports wildcards
282 - Added "show -pause" and "show -format dot"
283 - Added "show -color" support for cells
284 - Added "show -label" and "show -notitle"
285 - Added "dump -m" and "dump -n"
286 - Added "history" command
287 - Added "rename -hide"
288 - Added "connect" command
289 - Added "splitnets -driver"
290 - Added "opt_const -mux_undef"
291 - Added "opt_const -mux_bool"
292 - Added "opt_const -undriven"
293 - Added "opt -mux_undef -mux_bool -undriven -purge"
294 - Added "hierarchy -libdir"
295 - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
296 - Added "delete" command
297 - Added "dump -append"
298 - Added "setattr" and "setparam" commands
299 - Added "design -stash/-copy-from/-copy-to"
300 - Added "copy" command
301 - Added "splice" command