2 List of major changes and improvements between releases
3 =======================================================
6 Yosys 0.9 .. Yosys 0.9-dev
7 --------------------------
10 - Added "write_xaiger" backend
11 - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
12 - Added "synth_xilinx -abc9" (experimental)
13 - Added "synth_ice40 -abc9" (experimental)
14 - Added "synth -abc9" (experimental)
15 - Added "script -scriptwire
16 - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
17 - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
18 - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
19 - Renamed labels in synth_intel (e.g. bram -> map_bram)
20 - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
21 - Added automatic gzip decompression for frontends
22 - Added $_NMUX_ cell type
23 - Added automatic gzip compression (based on filename extension) for backends
24 - Improve attribute and parameter encoding in JSON to avoid ambiguities between
25 bit vectors and strings containing [01xz]*
26 - Improvements in pmgen: subpattern and recursive matches
27 - Added "opt_share" pass, run as part of "opt -full"
28 - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
29 - Removed "ice40_unlut"
30 - Improvements in pmgen: slices, choices, define, generate
31 - Added "xilinx_srl" for Xilinx shift register extraction
32 - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
34 Yosys 0.8 .. Yosys 0.8-dev
35 --------------------------
38 - Added $changed support to read_verilog
39 - Added "write_edif -attrprop"
40 - Added "ice40_unlut" pass
41 - Added "opt_lut" pass
42 - Added "synth_ice40 -relut"
43 - Added "synth_ice40 -noabc"
44 - Added "gate2lut.v" techmap rule
46 - Added "equiv_opt" pass
47 - Added "shregmap -tech xilinx"
48 - Added "read_aiger" frontend
49 - Added "muxcover -mux{4,8,16}=<cost>"
50 - Added "muxcover -dmux=<cost>"
51 - Added "muxcover -nopartial"
52 - Added "muxpack" pass
53 - Added "pmux2shiftx -norange"
54 - Added "synth_xilinx -nocarry"
55 - Added "synth_xilinx -nowidelut"
56 - Added "synth_ecp5 -nowidelut"
57 - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
58 - Fixed sign extension of unsized constants with 'bx and 'bz MSB
61 Yosys 0.7 .. Yosys 0.8
62 ----------------------
65 - Many bugfixes and small improvements
66 - Strip debug symbols from installed binary
67 - Replace -ignore_redef with -[no]overwrite in front-ends
68 - Added write_verilog hex dump support, add -nohex option
69 - Added "write_verilog -decimal"
70 - Added "scc -set_attr"
71 - Added "verilog_defines" command
72 - Remember defines from one read_verilog to next
73 - Added support for hierarchical defparam
74 - Added FIRRTL back-end
75 - Improved ABC default scripts
76 - Added "design -reset-vlog"
77 - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
78 - Added Verilog $rtoi and $itor support
79 - Added "check -initdrv"
80 - Added "read_blif -wideports"
81 - Added support for SystemVerilog "++" and "--" operators
82 - Added support for SystemVerilog unique, unique0, and priority case
83 - Added "write_edif" options for edif "flavors"
84 - Added support for resetall compiler directive
85 - Added simple C beck-end (bitwise combinatorical only atm)
86 - Added $_ANDNOT_ and $_ORNOT_ cell types
87 - Added cell library aliases to "abc -g"
88 - Added "setundef -anyseq"
89 - Added "chtype" command
90 - Added "design -import"
91 - Added "write_table" command
92 - Added "read_json" command
94 - Added "extract_fa" and "extract_reduce" commands
95 - Added "extract_counter" command
96 - Added "opt_demorgan" command
97 - Added support for $size and $bits SystemVerilog functions
98 - Added "blackbox" command
100 - Added support for editline as replacement for readline
101 - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
102 - Added "yosys -E" for creating Makefile dependencies files
103 - Added "synth -noshare"
104 - Added "memory_nordff"
105 - Added "setundef -undef -expose -anyconst"
106 - Added "expose -input"
107 - Added specify/specparam parser support (simply ignore them)
108 - Added "write_blif -inames -iattr"
109 - Added "hierarchy -simcheck"
110 - Added an option to statically link abc into yosys
111 - Added protobuf back-end
112 - Added BLIF parsing support for .conn and .cname
113 - Added read_verilog error checking for reg/wire/logic misuse
114 - Added "make coverage" and ENABLE_GCOV build option
116 * Changes in Yosys APIs
117 - Added ConstEval defaultval feature
118 - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
119 - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
120 - Added log_file_warning() and log_file_error() functions
122 * Formal Verification
123 - Added "write_aiger"
124 - Added "yosys-smtbmc --aig"
125 - Added "always <positive_int>" to .smtc format
126 - Added $cover cell type and support for cover properties
127 - Added $fair/$live cell type and support for liveness properties
128 - Added smtbmc support for memory vcd dumping
129 - Added "chformal" command
130 - Added "write_smt2 -stbv" and "write_smt2 -stdt"
131 - Fix equiv_simple, old behavior now available with "equiv_simple -short"
132 - Change to Yices2 as default SMT solver (it is GPL now)
133 - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
134 - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
135 - Added a brand new "write_btor" command for BTOR2
136 - Added clk2fflogic memory support and other improvements
137 - Added "async memory write" support to write_smt2
138 - Simulate clock toggling in yosys-smtbmc VCD output
139 - Added $allseq/$allconst cells for EA-solving
140 - Make -nordff the default in "prep"
141 - Added (* gclk *) attribute
142 - Added "async2sync" pass for single-clock designs with async resets
145 - Many improvements in Verific front-end
146 - Added proper handling of concurent SVA properties
147 - Map "const" and "rand const" to $anyseq/$anyconst
148 - Added "verific -import -flatten" and "verific -import -extnets"
149 - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
150 - Remove PSL support (because PSL has been removed in upstream Verific)
151 - Improve integration with "hierarchy" command design elaboration
152 - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
153 - Added simpilied "read" command that automatically uses verific if available
154 - Added "verific -set-<severity> <msg_id>.."
155 - Added "verific -work <libname>"
158 - Added initial Coolrunner-II support
159 - Added initial eASIC support
160 - Added initial ECP5 support
163 - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
166 - Add "synth_ice40 -vpr"
167 - Add "synth_ice40 -nodffe"
168 - Add "synth_ice40 -json"
169 - Add Support for UltraPlus cells
171 * MAX10 and Cyclone IV Support
172 - Added initial version of metacommand "synth_intel".
173 - Improved write_verilog command to produce VQM netlist for Quartus Prime.
174 - Added support for MAX10 FPGA family synthesis.
175 - Added support for Cyclone IV family synthesis.
176 - Added example of implementation for DE2i-150 board.
177 - Added example of implementation for MAX10 development kit.
178 - Added LFSR example from Asic World.
179 - Added "dffinit -highlow" for mapping to Intel primitives
182 Yosys 0.6 .. Yosys 0.7
183 ----------------------
186 - Added "yosys -D" feature
187 - Added support for installed plugins in $(DATDIR)/plugins/
188 - Renamed opt_const to opt_expr
189 - Renamed opt_share to opt_merge
190 - Added "prep -flatten" and "synth -flatten"
191 - Added "prep -auto-top" and "synth -auto-top"
192 - Using "mfs" and "lutpack" in ABC lut mapping
193 - Support for abstract modules in chparam
194 - Cleanup abstract modules at end of "hierarchy -top"
195 - Added tristate buffer support to iopadmap
196 - Added opt_expr support for div/mod by power-of-two
197 - Added "select -assert-min <N> -assert-max <N>"
198 - Added "attrmvcp" pass
199 - Added "attrmap" command
200 - Added "tee +INT -INT"
202 - Added "setparam -type"
203 - Added "shregmap" pass
204 - Added "setundef -init"
205 - Added "nlutmap -assert"
206 - Added $sop cell type and "abc -sop -I <num> -P <num>"
207 - Added "dc2" to default ABC scripts
209 - Added "insbuf" command
210 - Added "prep -nomem"
211 - Added "opt_rmdff -keepdc"
212 - Added "prep -nokeepdc"
213 - Added initial version of "synth_gowin"
214 - Added "fsm_expand -full"
215 - Added support for fsm_encoding="user"
216 - Many improvements in GreenPAK4 support
217 - Added black box modules for all Xilinx 7-series lib cells
218 - Added synth_ice40 support for latches via logic loops
219 - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
222 - Added ABCEXTERNAL and ABCURL make variables
223 - Added BINDIR, LIBDIR, and DATDIR make variables
224 - Added PKG_CONFIG make variable
225 - Added SEED make variable (for "make test")
226 - Added YOSYS_VER_STR make variable
227 - Updated min GCC requirement to GCC 4.8
228 - Updated required Bison version to Bison 3.x
231 - Added ast.h to exported headers
232 - Added ScriptPass helper class for script-like passes
233 - Added CellEdgesDatabase API
235 * Front-ends and Back-ends
236 - Added filename glob support to all front-ends
237 - Added avail (black-box) module params to ilang format
238 - Added $display %m support
239 - Added support for $stop Verilog system task
240 - Added support for SystemVerilog packages
241 - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
242 - Added support for "active high" and "active low" latches in read_blif and write_blif
243 - Use init value "2" for all uninitialized FFs in BLIF back-end
244 - Added "read_blif -sop"
245 - Added "write_blif -noalias"
246 - Added various write_blif options for VTR support
247 - write_json: also write module attributes.
248 - Added "write_verilog -nodec -nostr -defparam"
249 - Added "read_verilog -norestrict -assume-asserts"
250 - Added support for bus interfaces to "read_liberty -lib"
251 - Added liberty parser support for types within cell decls
252 - Added "write_verilog -renameprefix -v"
253 - Added "write_edif -nogndvcc"
255 * Formal Verification
256 - Support for hierarchical designs in smt2 back-end
257 - Yosys-smtbmc: Support for hierarchical VCD dumping
258 - Added $initstate cell type and vlog function
259 - Added $anyconst and $anyseq cell types and vlog functions
260 - Added printing of code loc of failed asserts to yosys-smtbmc
261 - Added memory_memx pass, "memory -memx", and "prep -memx"
262 - Added "proc_mux -ifx"
263 - Added "yosys-smtbmc -g"
264 - Deprecated "write_smt2 -regs" (by default on now)
265 - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
266 - Added support for memories to smtio.py
267 - Added "yosys-smtbmc --dump-vlogtb"
268 - Added "yosys-smtbmc --smtc --dump-smtc"
269 - Added "yosys-smtbmc --dump-all"
270 - Added assertpmux command
271 - Added "yosys-smtbmc --unroll"
272 - Added $past, $stable, $rose, $fell SVA functions
273 - Added "yosys-smtbmc --noinfo and --dummy"
274 - Added "yosys-smtbmc --noincr"
275 - Added "yosys-smtbmc --cex <filename>"
276 - Added $ff and $_FF_ cell types
277 - Added $global_clock verilog syntax support for creating $ff cells
281 Yosys 0.5 .. Yosys 0.6
282 ----------------------
285 - Added Contributor Covenant Code of Conduct
286 - Various improvements in dict<> and pool<>
287 - Added hashlib::mfp and refactored SigMap
288 - Improved support for reals as module parameters
289 - Various improvements in SMT2 back-end
290 - Added "keep_hierarchy" attribute
291 - Verilog front-end: define `BLACKBOX in -lib mode
292 - Added API for converting internal cells to AIGs
293 - Added ENABLE_LIBYOSYS Makefile option
294 - Removed "techmap -share_map" (use "-map +/filename" instead)
295 - Switched all Python scripts to Python 3
296 - Added support for $display()/$write() and $finish() to Verilog front-end
297 - Added "yosys-smtbmc" formal verification flow
298 - Added options for clang sanitizers to Makefile
300 * New commands and options
301 - Added "scc -expect <N> -nofeedback"
302 - Added "proc_dlatch"
304 - Added "select %xe %cie %coe %M %C %R"
305 - Added "sat -dump_json" (WaveJSON format)
306 - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
307 - Added "sat -stepsize" and "sat -tempinduct-step"
308 - Added "sat -show-regs -show-public -show-all"
309 - Added "write_json" (Native Yosys JSON format)
310 - Added "write_blif -attr"
315 - Added memory_bram "make_outreg" feature
316 - Added "splice -wires"
317 - Added "dff2dffe -direct-match"
318 - Added simplemap $lut support
320 - Added "opt_share -share_all"
322 - Added "write_smt2 -mem -regs -wires"
323 - Added "memory -nordff"
325 - Added "synth -nordff -noalumacc"
326 - Added "rename -top new_name"
327 - Added "opt_const -clkinv"
328 - Added "synth -nofsm"
329 - Added "miter -assert"
330 - Added "read_verilog -noautowire"
331 - Added "read_verilog -nodpi"
336 - Added "test_cell -noeval"
338 - Added "equiv_struct"
339 - Added "equiv_purge"
341 - Added "equiv_add -try -cell"
343 - Added "abc -g -luts"
345 - Added "write_blif -cname"
346 - Added "submod -copy"
348 - Added "stat -liberty"
350 * Synthesis metacommands
351 - Various improvements in synth_xilinx
352 - Added synth_ice40 and synth_greenpak4
353 - Added "prep" metacommand for "synthesis lite"
355 * Cell library changes
356 - Added cell types to "help" system
357 - Added $meminit cell type
358 - Added $assume cell type
359 - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
360 - Added $tribuf and $_TBUF_ cell types
361 - Added read-enable to memory model
364 - Various improvements in emscripten build
365 - Added alternative webworker-based JS API
366 - Added a few example applications
369 Yosys 0.4 .. Yosys 0.5
370 ----------------------
373 - Added log_warning()
374 - Added eval_select_args() and eval_select_op()
375 - Added cell->known(), cell->input(portname), cell->output(portname)
376 - Skip blackbox modules in design->selected_modules()
377 - Replaced std::map<> and std::set<> with dict<> and pool<>
378 - New SigSpec::extend() is what used to be SigSpec::extend_u0()
379 - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
381 * Cell library changes
382 - Added flip-flops with enable ($dffe etc.)
383 - Added $equiv cells for equivalence checking framework
386 - Updated ABC to hg rev 61ad5f908c03
387 - Added clock domain partitioning to ABC pass
388 - Improved plugin building (see "yosys-config --build")
389 - Added ENABLE_NDEBUG Makefile flag for high-performance builds
390 - Added "yosys -d", "yosys -L" and other driver improvements
391 - Added support for multi-bit (array) cell ports to "write_edif"
392 - Now printing most output to stdout, not stderr
393 - Added "onehot" attribute (set by "fsm_map")
394 - Various performance improvements
395 - Vastly improved Xilinx flow
396 - Added "make unsintall"
398 * Equivalence checking
399 - Added equivalence checking commands:
400 equiv_make equiv_simple equiv_status
401 equiv_induct equiv_miter
402 equiv_add equiv_remove
405 - Added "memory_bram" command
406 - Added BRAM support to Xilinx flow
408 * Other New Commands and Options
410 - Added "fsm -encfile"
411 - Added "dfflibmap -prepare"
412 - Added "write_blid -unbuf -undef -blackbox"
413 - Added "write_smt2" for writing SMT-LIBv2 files
414 - Added "test_cell -w -muxdiv"
415 - Added "select -read"
418 Yosys 0.3.0 .. Yosys 0.4
419 ------------------------
422 - Added support for mxe-based cross-builds for win32
423 - Added sourcecode-export as VisualStudio project
424 - Added experimental EMCC (JavaScript) support
427 - Added -sv option for SystemVerilog (and automatic *.sv file support)
428 - Added support for real-valued constants and constant expressions
429 - Added support for non-standard "via_celltype" attribute on task/func
430 - Added support for non-standard "module mod_name(...);" syntax
431 - Added support for non-standard """ macro bodies
432 - Added support for array with more than one dimension
433 - Added support for $readmemh and $readmemb
434 - Added support for DPI functions
436 * Changes in internal cell library
437 - Added $shift and $shiftx cell types
438 - Added $alu, $lcu, $fa and $macc cell types
439 - Removed $bu0 and $safe_pmux cell types
440 - $mem/$memwr WR_EN input is now a per-data-bit enable signal
441 - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
442 - Renamed ports of $lut cells (from I->O to A->Y)
443 - Renamed $_INV_ to $_NOT_
445 * Changes for simple synthesis flows
446 - There is now a "synth" command with a recommended default script
447 - Many improvements in synthesis of arithmetic functions to gates
448 - Multipliers and adders with many operands are using carry-save adder trees
449 - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
450 - Various new high-level optimizations on RTL netlist
451 - Various improvements in FSM optimization
452 - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
454 * Changes in internal APIs and RTLIL
455 - Added log_id() and log_cell() helper functions
456 - Added function-like cell creation helpers
457 - Added GetSize() function (like .size() but with int)
458 - Major refactoring of RTLIL::Module and related classes
459 - Major refactoring of RTLIL::SigSpec and related classes
460 - Now RTLIL::IdString is essentially an int
461 - Added macros for code coverage counters
462 - Added some Makefile magic for pretty make logs
463 - Added "kernel/yosys.h" with all the core definitions
464 - Changed a lot of code from FILE* to c++ streams
465 - Added RTLIL::Monitor API and "trace" command
466 - Added "Yosys" C++ namespace
468 * Changes relevant to SAT solving
469 - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
470 - Added native ezSAT support for vector shift ops
471 - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
473 * New commands (or large improvements to commands)
474 - Added "synth" command with default script
475 - Added "share" (finally some real resource sharing)
476 - Added "memory_share" (reduce number of ports on memories)
477 - Added "wreduce" and "alumacc" commands
478 - Added "opt -keepdc -fine -full -fast"
479 - Added some "test_*" commands
481 * Various other changes
482 - Added %D and %c select operators
483 - Added support for labels in yosys scripts
484 - Added support for here-documents in yosys scripts
485 - Support "+/" prefix for files from proc_share_dir
486 - Added "autoidx" statement to ilang language
487 - Switched from "yosys-svgviewer" to "xdot"
488 - Renamed "stdcells.v" to "techmap.v"
489 - Various bug fixes and small improvements
490 - Improved welcome and bye messages
493 Yosys 0.2.0 .. Yosys 0.3.0
494 --------------------------
496 * Driver program and overall behavior:
497 - Added "design -push" and "design -pop"
498 - Added "tee" command for redirecting log output
500 * Changes in the internal cell library:
501 - Added $dlatchsr and $_DLATCHSR_???_ cell types
503 * Improvements in Verilog frontend:
504 - Improved support for const functions (case, always, repeat)
505 - The generate..endgenerate keywords are now optional
506 - Added support for arrays of module instances
507 - Added support for "`default_nettype" directive
508 - Added support for "`line" directive
510 * Other front- and back-ends:
511 - Various changes to "write_blif" options
512 - Various improvements in EDIF backend
513 - Added "vhdl2verilog" pseudo-front-end
514 - Added "verific" pseudo-front-end
516 * Improvements in technology mapping:
517 - Added support for recursive techmap
518 - Added CONSTMSK and CONSTVAL features to techmap
519 - Added _TECHMAP_CONNMAP_*_ feature to techmap
520 - Added _TECHMAP_REPLACE_ feature to techmap
521 - Added "connwrappers" command for wrap-extract-unwrap method
522 - Added "extract -map %<design_name>" feature
523 - Added "extract -ignore_param ..." and "extract -ignore_parameters"
524 - Added "techmap -max_iter" option
526 * Improvements to "eval" and "sat" framework:
527 - Now include a copy of Minisat (with build fixes applied)
528 - Switched to Minisat::SimpSolver as SAT back-end
529 - Added "sat -dump_vcd" feature
530 - Added "sat -dump_cnf" feature
531 - Added "sat -initsteps <N>" feature
532 - Added "freduce -stop <N>" feature
533 - Added "freduce -dump <prefix>" feature
535 * Integration with ABC:
536 - Updated ABC rev to 7600ffb9340c
538 * Improvements in the internal APIs:
539 - Added RTLIL::Module::add... helper methods
540 - Various build fixes for OSX (Darwin) and OpenBSD
543 Yosys 0.1.0 .. Yosys 0.2.0
544 --------------------------
546 * Changes to the driver program:
547 - Added "yosys -h" and "yosys -H"
548 - Added support for backslash line continuation in scripts
549 - Added support for #-comments in same line as command
550 - Added "echo" and "log" commands
552 * Improvements in Verilog frontend:
553 - Added support for local registers in named blocks
554 - Added support for "case" in "generate" blocks
555 - Added support for $clog2 system function
556 - Added support for basic SystemVerilog assert statements
557 - Added preprocessor support for macro arguments
558 - Added preprocessor support for `elsif statement
559 - Added "verilog_defaults" command
560 - Added read_verilog -icells option
561 - Added support for constant sizes from parameters
562 - Added "read_verilog -setattr"
563 - Added support for function returning 'integer'
564 - Added limited support for function calls in parameter values
565 - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
567 * Other front- and back-ends:
569 - Added Liberty frontend
571 * Improvements in technology mapping:
572 - The "dfflibmap" command now strongly prefers solutions with
573 no inverters in clock paths
574 - The "dfflibmap" command now prefers cells with smaller area
575 - Added support for multiple -map options to techmap
576 - Added "dfflibmap" support for //-comments in liberty files
577 - Added "memory_unpack" command to revert "memory_collect"
578 - Added standard techmap rule "techmap -share_map pmux2mux.v"
579 - Added "iopadmap -bits"
580 - Added "setundef" command
581 - Added "hilomap" command
583 * Changes in the internal cell library:
584 - Major rewrite of simlib.v for better compatibility with other tools
585 - Added PRIORITY parameter to $memwr cells
586 - Added TRANSPARENT parameter to $memrd cells
587 - Added RD_TRANSPARENT parameter to $mem cells
588 - Added $bu0 cell (always 0-extend, even undef MSB)
589 - Added $assert cell type
590 - Added $slice and $concat cell types
592 * Integration with ABC:
593 - Updated ABC to hg rev 2058c8ccea68
594 - Tighter integration of ABC build with Yosys build. The make
595 targets 'make abc' and 'make install-abc' are now obsolete.
596 - Added support for passing FFs from one clock domain through ABC
597 - Now always use BLIF as exchange format with ABC
598 - Added support for "abc -script +<command_sequence>"
599 - Improved standard ABC recipe
600 - Added support for "keep" attribute to abc command
601 - Added "abc -dff / -clk / -keepff" options
603 * Improvements to "eval" and "sat" framework:
604 - Added support for "0" and "~0" in right-hand side -set expressions
605 - Added "eval -set-undef" and "eval -table"
606 - Added "sat -set-init" and "sat -set-init-*" for sequential problems
607 - Added undef support to SAT solver, incl. various new "sat" options
608 - Added correct support for === and !== for "eval" and "sat"
609 - Added "sat -tempinduct" (default -seq is now non-induction sequential)
610 - Added "sat -prove-asserts"
611 - Complete rewrite of the 'freduce' command
612 - Added "miter" command
613 - Added "sat -show-inputs" and "sat -show-outputs"
614 - Added "sat -ignore_unknown_cells" (now produce an error by default)
615 - Added "sat -falsify"
616 - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
617 - Added "expose" command
618 - Added support for @<sel_name> to sat and eval signal expressions
620 * Changes in the 'make test' framework and auxiliary test tools:
621 - Added autotest.sh -p and -f options
622 - Replaced autotest.sh ISIM support with XSIM support
623 - Added test cases for SAT framework
625 * Added "abbreviated IDs":
626 - Now $<something>$foo can be abbreviated as $foo.
627 - Usually this last part is a unique id (from RTLIL::autoidx)
628 - This abbreviated IDs are now also used in "show" output
630 * Other changes to selection framework:
631 - Now */ is optional in */<mode>:<arg> expressions
632 - Added "select -assert-none" and "select -assert-any"
633 - Added support for matching modules by attribute (A:<expr>)
634 - Added "select -none"
635 - Added support for r:<expr> pattern for matching cell parameters
636 - Added support for !=, <, <=, >=, > for attribute and parameter matching
637 - Added support for %s for selecting sub-modules
638 - Added support for %m for expanding selections to whole modules
639 - Added support for i:*, o:* and x:* pattern for selecting module ports
640 - Added support for s:<expr> pattern for matching wire width
641 - Added support for %a operation to select wire aliases
643 * Various other changes to commands and options:
644 - The "ls" command now supports wildcards
645 - Added "show -pause" and "show -format dot"
646 - Added "show -color" support for cells
647 - Added "show -label" and "show -notitle"
648 - Added "dump -m" and "dump -n"
649 - Added "history" command
650 - Added "rename -hide"
651 - Added "connect" command
652 - Added "splitnets -driver"
653 - Added "opt_const -mux_undef"
654 - Added "opt_const -mux_bool"
655 - Added "opt_const -undriven"
656 - Added "opt -mux_undef -mux_bool -undriven -purge"
657 - Added "hierarchy -libdir"
658 - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
659 - Added "delete" command
660 - Added "dump -append"
661 - Added "setattr" and "setparam" commands
662 - Added "design -stash/-copy-from/-copy-to"
663 - Added "copy" command
664 - Added "splice" command