CHANGELOG

   1
   2 List of major changes and improvements between releases
   3 =======================================================
   4
   5
   6 Yosys 0.4 .. Yosys 0.4+
   7 -----------------------
   8
   9  ... TBD ...
  10
  11
  12 Yosys 0.3.0 .. Yosys 0.4
  13 ------------------------
  14
  15  * Platform Support
  16      - Added support for mxe-based cross-builds for win32
  17      - Added sourcecode-export as VisualStudio project
  18      - Added experimental EMCC (JavaScript) support
  19
  20  * Verilog Frontend
  21      - Added -sv option for SystemVerilog (and automatic *.sv file support)
  22      - Added support for real-valued constants and constant expressions
  23      - Added support for non-standard "via_celltype" attribute on task/func
  24      - Added support for non-standard "module mod_name(...);" syntax
  25      - Added support for non-standard """ macro bodies
  26      - Added support for array with more than one dimension
  27      - Added support for $readmemh and $readmemb
  28      - Added support for DPI functions
  29
  30  * Changes in internal cell library
  31      - Added $shift and $shiftx cell types
  32      - Added $alu, $lcu, $fa and $macc cell types
  33      - Removed $bu0 and $safe_pmux cell types
  34      - $mem/$memwr WR_EN input is now a per-data-bit enable signal
  35      - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
  36      - Renamed ports of $lut cells (from I->O to A->Y)
  37      - Renamed $_INV_ to $_NOT_
  38
  39  * Changes for simple synthesis flows
  40      - There is now a "synth" command with a recommended default script
  41      - Many improvements in synthesis of arithmetic functions to gates
  42          - Multiplieres and adders with many operands are using carry-save adder trees
  43          - Remaining adders are now implemented using Brent–Kung carry look-ahead adders
  44      - Various new high-level optimizations on RTL netlist
  45      - Various improvements in FSM optimization
  46      - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
  47
  48  * Changes in internal APIs and RTLIL
  49      - Added log_id() and log_cell() helper functions
  50      - Added function-like cell creation helpers
  51      - Added GetSize() function (like .size() but with int)
  52      - Major refactoring of RTLIL::Module and related classes
  53      - Major refactoring of RTLIL::SigSpec and related classes
  54      - Now RTLIL::IdString is essentially an int
  55      - Added macros for code coverage counters
  56      - Added some Makefile magic for pretty make logs
  57      - Added "kernel/yosys.h" with all the core definitions
  58      - Chanded a lot of code from FILE* to c++ streams
  59      - Added RTLIL::Monitor API and "trace" command
  60      - Added "Yosys" C++ namespace
  61
  62  * Changes relevant to SAT solving
  63      - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
  64      - Added native ezSAT support for vector shift ops
  65      - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
  66
  67  * New commands (or large improvements to commands)
  68      - Added "synth" command with default script
  69      - Added "share" (finally some real resource sharing)
  70      - Added "memory_share" (reduce number of ports on memories)
  71      - Added "wreduce" and "alumacc" commands
  72      - Added "opt -keepdc -fine -full -fast"
  73      - Added some "test_*" commands
  74
  75  * Various other changes
  76      - Added %D and %c select operators
  77      - Added support for labels in yosys scripts
  78      - Added support for here-documents in yosys scripts
  79      - Support "+/" prefix for files from proc_share_dir
  80      - Added "autoidx" statement to ilang language
  81      - Switched from "yosys-svgviewer" to "xdot"
  82      - Renamed "stdcells.v" to "techmap.v"
  83      - Various bug fixes and small improvements
  84      - Improved welcome and bye messages
  85
  86
  87 Yosys 0.2.0 .. Yosys 0.3.0
  88 --------------------------
  89
  90  * Driver program and overall behavior:
  91      - Added "design -push" and "design -pop"
  92      - Added "tee" command for redirecting log output
  93
  94  * Changes in the internal cell library:
  95      - Added $dlatchsr and $_DLATCHSR_???_ cell types
  96
  97  * Improvements in Verilog frontend:
  98      - Improved support for const functions (case, always, repeat)
  99      - The generate..endgenerate keywords are now optional
 100      - Added support for arrays of module instances
 101      - Added support for "`default_nettype" directive
 102      - Added support for "`line" directive
 103
 104  * Other front- and back-ends:
 105      - Various changes to "write_blif" options
 106      - Various improvements in EDIF backend
 107      - Added "vhdl2verilog" pseudo-front-end
 108      - Added "verific" pseudo-front-end
 109
 110  * Improvements in technology mapping:
 111      - Added support for recursive techmap
 112      - Added CONSTMSK and CONSTVAL features to techmap
 113      - Added _TECHMAP_CONNMAP_*_ feature to techmap
 114      - Added _TECHMAP_REPLACE_ feature to techmap
 115      - Added "connwrappers" command for wrap-extract-unwrap method
 116      - Added "extract -map %<design_name>" feature
 117      - Added "extract -ignore_param ..." and "extract -ignore_parameters"
 118      - Added "techmap -max_iter" option
 119
 120  * Improvements to "eval" and "sat" framework:
 121      - Now include a copy of Minisat (with build fixes applied)
 122      - Switched to Minisat::SimpSolver as SAT back-end
 123      - Added "sat -dump_vcd" feature
 124      - Added "sat -dump_cnf" feature
 125      - Added "sat -initsteps <N>" feature
 126      - Added "freduce -stop <N>" feature
 127      - Added "fredure -dump <prefix>" feature
 128
 129  * Integration with ABC:
 130      - Updated ABC rev to 7600ffb9340c
 131
 132  * Improvements in the internal APIs:
 133      - Added RTLIL::Module::add... helper methods
 134      - Various build fixes for OSX (Darwin) and OpenBSD
 135
 136
 137 Yosys 0.1.0 .. Yosys 0.2.0
 138 --------------------------
 139
 140  * Changes to the driver program:
 141      - Added "yosys -h" and "yosys -H"
 142      - Added support for backslash line continuation in scripts
 143      - Added support for #-comments in same line as command
 144      - Added "echo" and "log" commands
 145
 146  * Improvements in Verilog frontend:
 147      - Added support for local registers in named blocks
 148      - Added support for "case" in "generate" blocks
 149      - Added support for $clog2 system function
 150      - Added support for basic SystemVerilog assert statements
 151      - Added preprocessor support for macro arguments
 152      - Added preprocessor support for `elsif statement
 153      - Added "verilog_defaults" command
 154      - Added read_verilog -icells option
 155      - Added support for constant sizes from parameters
 156      - Added "read_verilog -setattr"
 157      - Added support for function returning 'integer'
 158      - Added limited support for function calls in parameter values
 159      - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
 160
 161  * Other front- and back-ends:
 162      - Added BTOR backend
 163      - Added Liberty frontend
 164
 165  * Improvements in technology mapping:
 166      - The "dfflibmap" command now strongly prefers solutions with
 167            no inverters in clock paths
 168      - The "dfflibmap" command now prefers cells with smaller area
 169      - Added support for multiple -map options to techmap
 170      - Added "dfflibmap" support for //-comments in liberty files
 171      - Added "memory_unpack" command to revert "memory_collect"
 172      - Added standard techmap rule "techmap -share_map pmux2mux.v"
 173      - Added "iopadmap -bits"
 174      - Added "setundef" command
 175      - Added "hilomap" command
 176
 177  * Changes in the internal cell library:
 178      - Major rewrite of simlib.v for better compatibility with other tools
 179      - Added PRIORITY parameter to $memwr cells
 180      - Added TRANSPARENT parameter to $memrd cells
 181      - Added RD_TRANSPARENT parameter to $mem cells
 182      - Added $bu0 cell (always 0-extend, even undef MSB)
 183      - Added $assert cell type
 184      - Added $slice and $concat cell types
 185
 186  * Integration with ABC:
 187      - Updated ABC to hg rev 2058c8ccea68
 188      - Tighter integration of ABC build with Yosys build. The make
 189            targets 'make abc' and 'make install-abc' are now obsolete.
 190      - Added support for passing FFs from one clock domain through ABC
 191      - Now always use BLIF as exchange format with ABC
 192      - Added support for "abc -script +<command_sequence>"
 193      - Improved standard ABC recipe
 194      - Added support for "keep" attribute to abc command
 195      - Added "abc -dff / -clk / -keepff" options
 196
 197  * Improvements to "eval" and "sat" framework:
 198      - Added support for "0" and "~0" in right-hand side -set expressions
 199      - Added "eval -set-undef" and "eval -table"
 200      - Added "sat -set-init" and "sat -set-init-*" for sequential problems
 201      - Added undef support to SAT solver, incl. various new "sat" options
 202      - Added correct support for === and !== for "eval" and "sat"
 203      - Added "sat -tempinduct" (default -seq is now non-induction sequential)
 204      - Added "sat -prove-asserts"
 205      - Complete rewrite of the 'freduce' command
 206      - Added "miter" command
 207      - Added "sat -show-inputs" and "sat -show-outputs"
 208      - Added "sat -ignore_unknown_cells" (now produce an error by default)
 209      - Added "sat -falsify"
 210      - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
 211      - Added "expose" command
 212      - Added support for @<sel_name> to sat and eval signal expressions
 213
 214  * Changes in the 'make test' framework and auxilary test tools:
 215      - Added autotest.sh -p and -f options
 216      - Replaced autotest.sh ISIM support with XSIM support
 217      - Added test cases for SAT framework
 218
 219  * Added "abbreviated IDs":
 220      - Now $<something>$foo can be abbriviated as $foo.
 221      - Usually this last part is a unique id (from RTLIL::autoidx)
 222      - This abbreviated IDs are now also used in "show" output
 223
 224  * Other changes to selection framework:
 225      - Now */ is optional in */<mode>:<arg> expressions
 226      - Added "select -assert-none" and "select -assert-any"
 227      - Added support for matching modules by attribute (A:<expr>)
 228      - Added "select -none"
 229      - Added support for r:<expr> pattern for matching cell parameters
 230      - Added support for !=, <, <=, >=, > for attribute and parameter matching
 231      - Added support for %s for selecting sub-modules
 232      - Added support for %m for expanding selections to whole modules
 233      - Added support for i:*, o:* and x:* pattern for selecting module ports
 234      - Added support for s:<expr> pattern for matching wire width
 235      - Added support for %a operation to select wire aliases
 236
 237  * Various other changes to commands and options:
 238      - The "ls" command now supports wildcards
 239      - Added "show -pause" and "show -format dot"
 240      - Added "show -color" support for cells
 241      - Added "show -label" and "show -notitle"
 242      - Added "dump -m" and "dump -n"
 243      - Added "history" command
 244      - Added "rename -hide"
 245      - Added "connect" command
 246      - Added "splitnets -driver"
 247      - Added "opt_const -mux_undef"
 248      - Added "opt_const -mux_bool"
 249      - Added "opt_const -undriven"
 250      - Added "opt -mux_undef -mux_bool -undriven -purge"
 251      - Added "hierarchy -libdir"
 252      - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
 253      - Added "delete" command
 254      - Added "dump -append"
 255      - Added "setattr" and "setparam" commands
 256      - Added "design -stash/-copy-from/-copy-to"
 257      - Added "copy" command
 258      - Added "splice" command
 259