2 List of major changes and improvements between releases
3 =======================================================
6 Yosys 0.9 .. Yosys 0.9-dev
7 --------------------------
10 - Added "write_xaiger" backend
11 - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
12 - Added "synth_xilinx -abc9" (experimental)
13 - Added "synth_ice40 -abc9" (experimental)
14 - Added "synth -abc9" (experimental)
15 - Added "synth -keepdc"
16 - Added "script -scriptwire
19 Yosys 0.8 .. Yosys 0.8-dev
20 --------------------------
23 - Added $changed support to read_verilog
24 - Added "write_edif -attrprop"
25 - Added "ice40_unlut" pass
26 - Added "opt_lut" pass
27 - Added "synth_ice40 -relut"
28 - Added "synth_ice40 -noabc"
29 - Added "gate2lut.v" techmap rule
31 - Added "equiv_opt" pass
32 - Added "shregmap -tech xilinx"
33 - Added "read_aiger" frontend
34 - Added "muxcover -mux{4,8,16}=<cost>"
35 - Added "muxcover -dmux=<cost>"
36 - Added "muxcover -nopartial"
37 - Added "muxpack" pass
38 - Added "pmux2shiftx -norange"
39 - Added "synth_xilinx -nocarry"
40 - Added "synth_xilinx -nowidelut"
41 - Added "synth_ecp5 -nowidelut"
42 - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
43 - Fixed sign extension of unsized constants with 'bx and 'bz MSB
46 Yosys 0.7 .. Yosys 0.8
47 ----------------------
50 - Many bugfixes and small improvements
51 - Strip debug symbols from installed binary
52 - Replace -ignore_redef with -[no]overwrite in front-ends
53 - Added write_verilog hex dump support, add -nohex option
54 - Added "write_verilog -decimal"
55 - Added "scc -set_attr"
56 - Added "verilog_defines" command
57 - Remember defines from one read_verilog to next
58 - Added support for hierarchical defparam
59 - Added FIRRTL back-end
60 - Improved ABC default scripts
61 - Added "design -reset-vlog"
62 - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
63 - Added Verilog $rtoi and $itor support
64 - Added "check -initdrv"
65 - Added "read_blif -wideports"
66 - Added support for SystemVerilog "++" and "--" operators
67 - Added support for SystemVerilog unique, unique0, and priority case
68 - Added "write_edif" options for edif "flavors"
69 - Added support for resetall compiler directive
70 - Added simple C beck-end (bitwise combinatorical only atm)
71 - Added $_ANDNOT_ and $_ORNOT_ cell types
72 - Added cell library aliases to "abc -g"
73 - Added "setundef -anyseq"
74 - Added "chtype" command
75 - Added "design -import"
76 - Added "write_table" command
77 - Added "read_json" command
79 - Added "extract_fa" and "extract_reduce" commands
80 - Added "extract_counter" command
81 - Added "opt_demorgan" command
82 - Added support for $size and $bits SystemVerilog functions
83 - Added "blackbox" command
85 - Added support for editline as replacement for readline
86 - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
87 - Added "yosys -E" for creating Makefile dependencies files
88 - Added "synth -noshare"
89 - Added "memory_nordff"
90 - Added "setundef -undef -expose -anyconst"
91 - Added "expose -input"
92 - Added specify/specparam parser support (simply ignore them)
93 - Added "write_blif -inames -iattr"
94 - Added "hierarchy -simcheck"
95 - Added an option to statically link abc into yosys
96 - Added protobuf back-end
97 - Added BLIF parsing support for .conn and .cname
98 - Added read_verilog error checking for reg/wire/logic misuse
99 - Added "make coverage" and ENABLE_GCOV build option
101 * Changes in Yosys APIs
102 - Added ConstEval defaultval feature
103 - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
104 - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
105 - Added log_file_warning() and log_file_error() functions
107 * Formal Verification
108 - Added "write_aiger"
109 - Added "yosys-smtbmc --aig"
110 - Added "always <positive_int>" to .smtc format
111 - Added $cover cell type and support for cover properties
112 - Added $fair/$live cell type and support for liveness properties
113 - Added smtbmc support for memory vcd dumping
114 - Added "chformal" command
115 - Added "write_smt2 -stbv" and "write_smt2 -stdt"
116 - Fix equiv_simple, old behavior now available with "equiv_simple -short"
117 - Change to Yices2 as default SMT solver (it is GPL now)
118 - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
119 - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
120 - Added a brand new "write_btor" command for BTOR2
121 - Added clk2fflogic memory support and other improvements
122 - Added "async memory write" support to write_smt2
123 - Simulate clock toggling in yosys-smtbmc VCD output
124 - Added $allseq/$allconst cells for EA-solving
125 - Make -nordff the default in "prep"
126 - Added (* gclk *) attribute
127 - Added "async2sync" pass for single-clock designs with async resets
130 - Many improvements in Verific front-end
131 - Added proper handling of concurent SVA properties
132 - Map "const" and "rand const" to $anyseq/$anyconst
133 - Added "verific -import -flatten" and "verific -import -extnets"
134 - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
135 - Remove PSL support (because PSL has been removed in upstream Verific)
136 - Improve integration with "hierarchy" command design elaboration
137 - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
138 - Added simpilied "read" command that automatically uses verific if available
139 - Added "verific -set-<severity> <msg_id>.."
140 - Added "verific -work <libname>"
143 - Added initial Coolrunner-II support
144 - Added initial eASIC support
145 - Added initial ECP5 support
148 - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
151 - Add "synth_ice40 -vpr"
152 - Add "synth_ice40 -nodffe"
153 - Add "synth_ice40 -json"
154 - Add Support for UltraPlus cells
156 * MAX10 and Cyclone IV Support
157 - Added initial version of metacommand "synth_intel".
158 - Improved write_verilog command to produce VQM netlist for Quartus Prime.
159 - Added support for MAX10 FPGA family synthesis.
160 - Added support for Cyclone IV family synthesis.
161 - Added example of implementation for DE2i-150 board.
162 - Added example of implementation for MAX10 development kit.
163 - Added LFSR example from Asic World.
164 - Added "dffinit -highlow" for mapping to Intel primitives
167 Yosys 0.6 .. Yosys 0.7
168 ----------------------
171 - Added "yosys -D" feature
172 - Added support for installed plugins in $(DATDIR)/plugins/
173 - Renamed opt_const to opt_expr
174 - Renamed opt_share to opt_merge
175 - Added "prep -flatten" and "synth -flatten"
176 - Added "prep -auto-top" and "synth -auto-top"
177 - Using "mfs" and "lutpack" in ABC lut mapping
178 - Support for abstract modules in chparam
179 - Cleanup abstract modules at end of "hierarchy -top"
180 - Added tristate buffer support to iopadmap
181 - Added opt_expr support for div/mod by power-of-two
182 - Added "select -assert-min <N> -assert-max <N>"
183 - Added "attrmvcp" pass
184 - Added "attrmap" command
185 - Added "tee +INT -INT"
187 - Added "setparam -type"
188 - Added "shregmap" pass
189 - Added "setundef -init"
190 - Added "nlutmap -assert"
191 - Added $sop cell type and "abc -sop -I <num> -P <num>"
192 - Added "dc2" to default ABC scripts
194 - Added "insbuf" command
195 - Added "prep -nomem"
196 - Added "opt_rmdff -keepdc"
197 - Added "prep -nokeepdc"
198 - Added initial version of "synth_gowin"
199 - Added "fsm_expand -full"
200 - Added support for fsm_encoding="user"
201 - Many improvements in GreenPAK4 support
202 - Added black box modules for all Xilinx 7-series lib cells
203 - Added synth_ice40 support for latches via logic loops
204 - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
207 - Added ABCEXTERNAL and ABCURL make variables
208 - Added BINDIR, LIBDIR, and DATDIR make variables
209 - Added PKG_CONFIG make variable
210 - Added SEED make variable (for "make test")
211 - Added YOSYS_VER_STR make variable
212 - Updated min GCC requirement to GCC 4.8
213 - Updated required Bison version to Bison 3.x
216 - Added ast.h to exported headers
217 - Added ScriptPass helper class for script-like passes
218 - Added CellEdgesDatabase API
220 * Front-ends and Back-ends
221 - Added filename glob support to all front-ends
222 - Added avail (black-box) module params to ilang format
223 - Added $display %m support
224 - Added support for $stop Verilog system task
225 - Added support for SystemVerilog packages
226 - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
227 - Added support for "active high" and "active low" latches in read_blif and write_blif
228 - Use init value "2" for all uninitialized FFs in BLIF back-end
229 - Added "read_blif -sop"
230 - Added "write_blif -noalias"
231 - Added various write_blif options for VTR support
232 - write_json: also write module attributes.
233 - Added "write_verilog -nodec -nostr -defparam"
234 - Added "read_verilog -norestrict -assume-asserts"
235 - Added support for bus interfaces to "read_liberty -lib"
236 - Added liberty parser support for types within cell decls
237 - Added "write_verilog -renameprefix -v"
238 - Added "write_edif -nogndvcc"
240 * Formal Verification
241 - Support for hierarchical designs in smt2 back-end
242 - Yosys-smtbmc: Support for hierarchical VCD dumping
243 - Added $initstate cell type and vlog function
244 - Added $anyconst and $anyseq cell types and vlog functions
245 - Added printing of code loc of failed asserts to yosys-smtbmc
246 - Added memory_memx pass, "memory -memx", and "prep -memx"
247 - Added "proc_mux -ifx"
248 - Added "yosys-smtbmc -g"
249 - Deprecated "write_smt2 -regs" (by default on now)
250 - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
251 - Added support for memories to smtio.py
252 - Added "yosys-smtbmc --dump-vlogtb"
253 - Added "yosys-smtbmc --smtc --dump-smtc"
254 - Added "yosys-smtbmc --dump-all"
255 - Added assertpmux command
256 - Added "yosys-smtbmc --unroll"
257 - Added $past, $stable, $rose, $fell SVA functions
258 - Added "yosys-smtbmc --noinfo and --dummy"
259 - Added "yosys-smtbmc --noincr"
260 - Added "yosys-smtbmc --cex <filename>"
261 - Added $ff and $_FF_ cell types
262 - Added $global_clock verilog syntax support for creating $ff cells
266 Yosys 0.5 .. Yosys 0.6
267 ----------------------
270 - Added Contributor Covenant Code of Conduct
271 - Various improvements in dict<> and pool<>
272 - Added hashlib::mfp and refactored SigMap
273 - Improved support for reals as module parameters
274 - Various improvements in SMT2 back-end
275 - Added "keep_hierarchy" attribute
276 - Verilog front-end: define `BLACKBOX in -lib mode
277 - Added API for converting internal cells to AIGs
278 - Added ENABLE_LIBYOSYS Makefile option
279 - Removed "techmap -share_map" (use "-map +/filename" instead)
280 - Switched all Python scripts to Python 3
281 - Added support for $display()/$write() and $finish() to Verilog front-end
282 - Added "yosys-smtbmc" formal verification flow
283 - Added options for clang sanitizers to Makefile
285 * New commands and options
286 - Added "scc -expect <N> -nofeedback"
287 - Added "proc_dlatch"
289 - Added "select %xe %cie %coe %M %C %R"
290 - Added "sat -dump_json" (WaveJSON format)
291 - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
292 - Added "sat -stepsize" and "sat -tempinduct-step"
293 - Added "sat -show-regs -show-public -show-all"
294 - Added "write_json" (Native Yosys JSON format)
295 - Added "write_blif -attr"
300 - Added memory_bram "make_outreg" feature
301 - Added "splice -wires"
302 - Added "dff2dffe -direct-match"
303 - Added simplemap $lut support
305 - Added "opt_share -share_all"
307 - Added "write_smt2 -mem -regs -wires"
308 - Added "memory -nordff"
310 - Added "synth -nordff -noalumacc"
311 - Added "rename -top new_name"
312 - Added "opt_const -clkinv"
313 - Added "synth -nofsm"
314 - Added "miter -assert"
315 - Added "read_verilog -noautowire"
316 - Added "read_verilog -nodpi"
321 - Added "test_cell -noeval"
323 - Added "equiv_struct"
324 - Added "equiv_purge"
326 - Added "equiv_add -try -cell"
328 - Added "abc -g -luts"
330 - Added "write_blif -cname"
331 - Added "submod -copy"
333 - Added "stat -liberty"
335 * Synthesis metacommands
336 - Various improvements in synth_xilinx
337 - Added synth_ice40 and synth_greenpak4
338 - Added "prep" metacommand for "synthesis lite"
340 * Cell library changes
341 - Added cell types to "help" system
342 - Added $meminit cell type
343 - Added $assume cell type
344 - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
345 - Added $tribuf and $_TBUF_ cell types
346 - Added read-enable to memory model
349 - Various improvements in emscripten build
350 - Added alternative webworker-based JS API
351 - Added a few example applications
354 Yosys 0.4 .. Yosys 0.5
355 ----------------------
358 - Added log_warning()
359 - Added eval_select_args() and eval_select_op()
360 - Added cell->known(), cell->input(portname), cell->output(portname)
361 - Skip blackbox modules in design->selected_modules()
362 - Replaced std::map<> and std::set<> with dict<> and pool<>
363 - New SigSpec::extend() is what used to be SigSpec::extend_u0()
364 - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
366 * Cell library changes
367 - Added flip-flops with enable ($dffe etc.)
368 - Added $equiv cells for equivalence checking framework
371 - Updated ABC to hg rev 61ad5f908c03
372 - Added clock domain partitioning to ABC pass
373 - Improved plugin building (see "yosys-config --build")
374 - Added ENABLE_NDEBUG Makefile flag for high-performance builds
375 - Added "yosys -d", "yosys -L" and other driver improvements
376 - Added support for multi-bit (array) cell ports to "write_edif"
377 - Now printing most output to stdout, not stderr
378 - Added "onehot" attribute (set by "fsm_map")
379 - Various performance improvements
380 - Vastly improved Xilinx flow
381 - Added "make unsintall"
383 * Equivalence checking
384 - Added equivalence checking commands:
385 equiv_make equiv_simple equiv_status
386 equiv_induct equiv_miter
387 equiv_add equiv_remove
390 - Added "memory_bram" command
391 - Added BRAM support to Xilinx flow
393 * Other New Commands and Options
395 - Added "fsm -encfile"
396 - Added "dfflibmap -prepare"
397 - Added "write_blid -unbuf -undef -blackbox"
398 - Added "write_smt2" for writing SMT-LIBv2 files
399 - Added "test_cell -w -muxdiv"
400 - Added "select -read"
403 Yosys 0.3.0 .. Yosys 0.4
404 ------------------------
407 - Added support for mxe-based cross-builds for win32
408 - Added sourcecode-export as VisualStudio project
409 - Added experimental EMCC (JavaScript) support
412 - Added -sv option for SystemVerilog (and automatic *.sv file support)
413 - Added support for real-valued constants and constant expressions
414 - Added support for non-standard "via_celltype" attribute on task/func
415 - Added support for non-standard "module mod_name(...);" syntax
416 - Added support for non-standard """ macro bodies
417 - Added support for array with more than one dimension
418 - Added support for $readmemh and $readmemb
419 - Added support for DPI functions
421 * Changes in internal cell library
422 - Added $shift and $shiftx cell types
423 - Added $alu, $lcu, $fa and $macc cell types
424 - Removed $bu0 and $safe_pmux cell types
425 - $mem/$memwr WR_EN input is now a per-data-bit enable signal
426 - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
427 - Renamed ports of $lut cells (from I->O to A->Y)
428 - Renamed $_INV_ to $_NOT_
430 * Changes for simple synthesis flows
431 - There is now a "synth" command with a recommended default script
432 - Many improvements in synthesis of arithmetic functions to gates
433 - Multipliers and adders with many operands are using carry-save adder trees
434 - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
435 - Various new high-level optimizations on RTL netlist
436 - Various improvements in FSM optimization
437 - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
439 * Changes in internal APIs and RTLIL
440 - Added log_id() and log_cell() helper functions
441 - Added function-like cell creation helpers
442 - Added GetSize() function (like .size() but with int)
443 - Major refactoring of RTLIL::Module and related classes
444 - Major refactoring of RTLIL::SigSpec and related classes
445 - Now RTLIL::IdString is essentially an int
446 - Added macros for code coverage counters
447 - Added some Makefile magic for pretty make logs
448 - Added "kernel/yosys.h" with all the core definitions
449 - Changed a lot of code from FILE* to c++ streams
450 - Added RTLIL::Monitor API and "trace" command
451 - Added "Yosys" C++ namespace
453 * Changes relevant to SAT solving
454 - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
455 - Added native ezSAT support for vector shift ops
456 - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
458 * New commands (or large improvements to commands)
459 - Added "synth" command with default script
460 - Added "share" (finally some real resource sharing)
461 - Added "memory_share" (reduce number of ports on memories)
462 - Added "wreduce" and "alumacc" commands
463 - Added "opt -keepdc -fine -full -fast"
464 - Added some "test_*" commands
466 * Various other changes
467 - Added %D and %c select operators
468 - Added support for labels in yosys scripts
469 - Added support for here-documents in yosys scripts
470 - Support "+/" prefix for files from proc_share_dir
471 - Added "autoidx" statement to ilang language
472 - Switched from "yosys-svgviewer" to "xdot"
473 - Renamed "stdcells.v" to "techmap.v"
474 - Various bug fixes and small improvements
475 - Improved welcome and bye messages
478 Yosys 0.2.0 .. Yosys 0.3.0
479 --------------------------
481 * Driver program and overall behavior:
482 - Added "design -push" and "design -pop"
483 - Added "tee" command for redirecting log output
485 * Changes in the internal cell library:
486 - Added $dlatchsr and $_DLATCHSR_???_ cell types
488 * Improvements in Verilog frontend:
489 - Improved support for const functions (case, always, repeat)
490 - The generate..endgenerate keywords are now optional
491 - Added support for arrays of module instances
492 - Added support for "`default_nettype" directive
493 - Added support for "`line" directive
495 * Other front- and back-ends:
496 - Various changes to "write_blif" options
497 - Various improvements in EDIF backend
498 - Added "vhdl2verilog" pseudo-front-end
499 - Added "verific" pseudo-front-end
501 * Improvements in technology mapping:
502 - Added support for recursive techmap
503 - Added CONSTMSK and CONSTVAL features to techmap
504 - Added _TECHMAP_CONNMAP_*_ feature to techmap
505 - Added _TECHMAP_REPLACE_ feature to techmap
506 - Added "connwrappers" command for wrap-extract-unwrap method
507 - Added "extract -map %<design_name>" feature
508 - Added "extract -ignore_param ..." and "extract -ignore_parameters"
509 - Added "techmap -max_iter" option
511 * Improvements to "eval" and "sat" framework:
512 - Now include a copy of Minisat (with build fixes applied)
513 - Switched to Minisat::SimpSolver as SAT back-end
514 - Added "sat -dump_vcd" feature
515 - Added "sat -dump_cnf" feature
516 - Added "sat -initsteps <N>" feature
517 - Added "freduce -stop <N>" feature
518 - Added "freduce -dump <prefix>" feature
520 * Integration with ABC:
521 - Updated ABC rev to 7600ffb9340c
523 * Improvements in the internal APIs:
524 - Added RTLIL::Module::add... helper methods
525 - Various build fixes for OSX (Darwin) and OpenBSD
528 Yosys 0.1.0 .. Yosys 0.2.0
529 --------------------------
531 * Changes to the driver program:
532 - Added "yosys -h" and "yosys -H"
533 - Added support for backslash line continuation in scripts
534 - Added support for #-comments in same line as command
535 - Added "echo" and "log" commands
537 * Improvements in Verilog frontend:
538 - Added support for local registers in named blocks
539 - Added support for "case" in "generate" blocks
540 - Added support for $clog2 system function
541 - Added support for basic SystemVerilog assert statements
542 - Added preprocessor support for macro arguments
543 - Added preprocessor support for `elsif statement
544 - Added "verilog_defaults" command
545 - Added read_verilog -icells option
546 - Added support for constant sizes from parameters
547 - Added "read_verilog -setattr"
548 - Added support for function returning 'integer'
549 - Added limited support for function calls in parameter values
550 - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
552 * Other front- and back-ends:
554 - Added Liberty frontend
556 * Improvements in technology mapping:
557 - The "dfflibmap" command now strongly prefers solutions with
558 no inverters in clock paths
559 - The "dfflibmap" command now prefers cells with smaller area
560 - Added support for multiple -map options to techmap
561 - Added "dfflibmap" support for //-comments in liberty files
562 - Added "memory_unpack" command to revert "memory_collect"
563 - Added standard techmap rule "techmap -share_map pmux2mux.v"
564 - Added "iopadmap -bits"
565 - Added "setundef" command
566 - Added "hilomap" command
568 * Changes in the internal cell library:
569 - Major rewrite of simlib.v for better compatibility with other tools
570 - Added PRIORITY parameter to $memwr cells
571 - Added TRANSPARENT parameter to $memrd cells
572 - Added RD_TRANSPARENT parameter to $mem cells
573 - Added $bu0 cell (always 0-extend, even undef MSB)
574 - Added $assert cell type
575 - Added $slice and $concat cell types
577 * Integration with ABC:
578 - Updated ABC to hg rev 2058c8ccea68
579 - Tighter integration of ABC build with Yosys build. The make
580 targets 'make abc' and 'make install-abc' are now obsolete.
581 - Added support for passing FFs from one clock domain through ABC
582 - Now always use BLIF as exchange format with ABC
583 - Added support for "abc -script +<command_sequence>"
584 - Improved standard ABC recipe
585 - Added support for "keep" attribute to abc command
586 - Added "abc -dff / -clk / -keepff" options
588 * Improvements to "eval" and "sat" framework:
589 - Added support for "0" and "~0" in right-hand side -set expressions
590 - Added "eval -set-undef" and "eval -table"
591 - Added "sat -set-init" and "sat -set-init-*" for sequential problems
592 - Added undef support to SAT solver, incl. various new "sat" options
593 - Added correct support for === and !== for "eval" and "sat"
594 - Added "sat -tempinduct" (default -seq is now non-induction sequential)
595 - Added "sat -prove-asserts"
596 - Complete rewrite of the 'freduce' command
597 - Added "miter" command
598 - Added "sat -show-inputs" and "sat -show-outputs"
599 - Added "sat -ignore_unknown_cells" (now produce an error by default)
600 - Added "sat -falsify"
601 - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
602 - Added "expose" command
603 - Added support for @<sel_name> to sat and eval signal expressions
605 * Changes in the 'make test' framework and auxiliary test tools:
606 - Added autotest.sh -p and -f options
607 - Replaced autotest.sh ISIM support with XSIM support
608 - Added test cases for SAT framework
610 * Added "abbreviated IDs":
611 - Now $<something>$foo can be abbreviated as $foo.
612 - Usually this last part is a unique id (from RTLIL::autoidx)
613 - This abbreviated IDs are now also used in "show" output
615 * Other changes to selection framework:
616 - Now */ is optional in */<mode>:<arg> expressions
617 - Added "select -assert-none" and "select -assert-any"
618 - Added support for matching modules by attribute (A:<expr>)
619 - Added "select -none"
620 - Added support for r:<expr> pattern for matching cell parameters
621 - Added support for !=, <, <=, >=, > for attribute and parameter matching
622 - Added support for %s for selecting sub-modules
623 - Added support for %m for expanding selections to whole modules
624 - Added support for i:*, o:* and x:* pattern for selecting module ports
625 - Added support for s:<expr> pattern for matching wire width
626 - Added support for %a operation to select wire aliases
628 * Various other changes to commands and options:
629 - The "ls" command now supports wildcards
630 - Added "show -pause" and "show -format dot"
631 - Added "show -color" support for cells
632 - Added "show -label" and "show -notitle"
633 - Added "dump -m" and "dump -n"
634 - Added "history" command
635 - Added "rename -hide"
636 - Added "connect" command
637 - Added "splitnets -driver"
638 - Added "opt_const -mux_undef"
639 - Added "opt_const -mux_bool"
640 - Added "opt_const -undriven"
641 - Added "opt -mux_undef -mux_bool -undriven -purge"
642 - Added "hierarchy -libdir"
643 - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
644 - Added "delete" command
645 - Added "dump -append"
646 - Added "setattr" and "setparam" commands
647 - Added "design -stash/-copy-from/-copy-to"
648 - Added "copy" command
649 - Added "splice" command