CHANGELOG

   1
   2 List of major changes and improvements between releases
   3 =======================================================
   4
   5 Yosys 0.10 .. Yosys 0.10-dev
   6 --------------------------
   7
   8  * Various
   9     - Added $aldff and $aldffe (flip-flops with async load) cells
  10
  11  * SystemVerilog
  12     - Fixed an issue which prevented writing directly to a memory word via a
  13       connection to an output port
  14     - Fixed an issue which prevented unbased unsized literals (e.g., `'1`) from
  15       filling the width of a cell input
  16     - Fixed an issue where connecting a slice covering the entirety of a signed
  17       signal to a cell input would cause a failed assertion
  18
  19  * Verific support
  20     - Importer support for {PRIM,WIDE_OPER}_DFF
  21     - Importer support for PRIM_BUFIF1
  22     - Option to use Verific without VHDL support
  23     - Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
  24
  25 Yosys 0.9 .. Yosys 0.10
  26 --------------------------
  27
  28  * Various
  29     - Added automatic gzip decompression for frontends
  30     - Added $_NMUX_ cell type
  31     - Added automatic gzip compression (based on filename extension) for backends
  32     - Improve attribute and parameter encoding in JSON to avoid ambiguities between
  33       bit vectors and strings containing [01xz]*
  34     - Improvements in pmgen: subpattern and recursive matches
  35     - Support explicit FIRRTL properties
  36     - Improvements in pmgen: slices, choices, define, generate
  37     - Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
  38     - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
  39     - Added new frontend: rpc
  40     - Added --version and -version as aliases for -V
  41     - Improve yosys-smtbmc "solver not found" handling
  42     - Improved support of $readmem[hb] Memory Content File inclusion
  43     - Added CXXRTL backend
  44     - Use YosysHQ/abc instead of upstream berkeley-abc/abc
  45     - Added WASI platform support.
  46     - Added extmodule support to firrtl backend
  47     - Added $divfloor and $modfloor cells
  48     - Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
  49     - Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
  50     - Added firrtl backend support for generic parameters in blackbox components
  51     - Added $meminit_v2 cells (with support for write mask)
  52     - Added $mem_v2, $memrd_v2, $memwr_v2, with the following features:
  53       - write priority masks, per write/write port pair
  54       - transparency and undefined collision behavior masks, per read/write port pair
  55       - read port reset and initialization
  56       - wide ports (accessing a naturally aligned power-of-two number of memory cells)
  57
  58  * New commands and options
  59     - Added "write_xaiger" backend
  60     - Added "read_xaiger"
  61     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
  62     - Added "synth -abc9" (experimental)
  63     - Added "script -scriptwire"
  64     - Added "clkbufmap" pass
  65     - Added "extractinv" pass and "invertible_pin" attribute
  66     - Added "proc_clean -quiet"
  67     - Added "proc_prune" pass
  68     - Added "stat -tech cmos"
  69     - Added "opt_share" pass, run as part of "opt -full"
  70     - Added "-match-init" option to "dff2dffs" pass
  71     - Added "equiv_opt -multiclock"
  72     - Added "techmap_autopurge" support to techmap
  73     - Added "add -mod <modname[s]>"
  74     - Added "paramap" pass
  75     - Added "portlist" command
  76     - Added "check -mapped"
  77     - Added "check -allow-tbuf"
  78     - Added "autoname" pass
  79     - Added "write_verilog -extmem"
  80     - Added "opt_mem" pass
  81     - Added "scratchpad" pass
  82     - Added "fminit" pass
  83     - Added "opt_lut_ins" pass
  84     - Added "logger" pass
  85     - Added "show -nobg"
  86     - Added "exec" command
  87     - Added "design -delete"
  88     - Added "design -push-copy"
  89     - Added "qbfsat" command
  90     - Added "select -unset"
  91     - Added "dfflegalize" pass
  92     - Removed "opt_expr -clkinv" option, made it the default
  93     - Added "proc -nomux
  94     - Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass
  95
  96  * SystemVerilog
  97     - Added checking of always block types (always_comb, always_latch and always_ff)
  98     - Added support for wildcard port connections (.*)
  99     - Added support for enum typedefs
 100     - Added support for structs and packed unions.
 101     - Allow constant function calls in for loops and generate if and case
 102     - Added support for static cast
 103     - Added support for logic typed parameters
 104     - Fixed generate scoping issues
 105     - Added support for real-valued parameters
 106     - Allow localparams in constant functions
 107     - Module name scope support
 108     - Support recursive functions using ternary expressions
 109     - Extended support for integer types
 110     - Support for parameters without default values
 111     - Allow globals in one file to depend on globals in another
 112     - Added support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
 113     - Added support for parsing the 'bind' construct
 114     - support declaration in procedural for initialization
 115     - support declaration in generate for initialization
 116     - Support wand and wor of data types
 117
 118  * Verific support
 119     - Added "verific -L"
 120     - Add Verific SVA support for "always" properties
 121     - Add Verific support for SVA nexttime properties
 122     - Improve handling of verific primitives in "verific -import -V" mode
 123     - Import attributes for wires
 124     - Support VHDL enums
 125     - Added support for command files
 126
 127  * New back-ends
 128     - Added initial EFINIX support
 129     - Added Intel ALM: alternative synthesis for Intel FPGAs
 130     - Added initial Nexus support
 131     - Added initial MachXO2 support
 132     - Added initial QuickLogic PolarPro 3 support
 133
 134  * ECP5 support
 135     - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 136     - Added "synth_ecp5 -abc9" (experimental)
 137     - Added "synth_ecp5 -nowidelut"
 138     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
 139
 140  * iCE40 support
 141     - Added "synth_ice40 -abc9" (experimental)
 142     - Added "synth_ice40 -device"
 143     - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 144     - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
 145     - Removed "ice40_unlut"
 146     - Added "ice40_dsp" for Lattice iCE40 DSP packing
 147     - "synth_ice40 -dsp" to infer DSP blocks
 148
 149  * Xilinx support
 150     - Added "synth_xilinx -abc9" (experimental)
 151     - Added "synth_xilinx -nocarry"
 152     - Added "synth_xilinx -nowidelut"
 153     - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
 154     - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
 155     - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
 156     - Added "synth_xilinx -ise" (experimental)
 157     - Added "synth_xilinx -iopad"
 158     - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
 159     - Added "xilinx_srl" for Xilinx shift register extraction
 160     - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
 161     - Added "xilinx_dsp" for Xilinx DSP packing
 162     - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
 163     - Added latch support to synth_xilinx
 164     - Added support for flip-flops with synchronous reset to synth_xilinx
 165     - Added support for flip-flops with reset and enable to synth_xilinx
 166     - Added "xilinx_dffopt" pass
 167     - Added "synth_xilinx -dff"
 168
 169  * Intel support
 170     - Renamed labels in synth_intel (e.g. bram -> map_bram)
 171     - synth_intel: cyclone10 -> cyclone10lp, a10gx -> arria10gx
 172     - Added "intel_alm -abc9" (experimental)
 173
 174  * CoolRunner2 support
 175     - Separate and improve buffer cell insertion pass
 176     - Use extract_counter to optimize counters
 177
 178 Yosys 0.8 .. Yosys 0.9
 179 ----------------------
 180
 181  * Various
 182     - Many bugfixes and small improvements
 183     - Added support for SystemVerilog interfaces and modports
 184     - Added "write_edif -attrprop"
 185     - Added "opt_lut" pass
 186     - Added "gate2lut.v" techmap rule
 187     - Added "rename -src"
 188     - Added "equiv_opt" pass
 189     - Added "flowmap" LUT mapping pass
 190     - Added "rename -wire" to rename cells based on the wires they drive
 191     - Added "bugpoint" for creating minimised testcases
 192     - Added "write_edif -gndvccy"
 193     - "write_verilog" to escape Verilog keywords
 194     - Fixed sign handling of real constants
 195     - "write_verilog" to write initial statement for initial flop state
 196     - Added pmgen pattern matcher generator
 197     - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
 198     - Added "setundef -params" to replace undefined cell parameters
 199     - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
 200     - Fixed handling of defparam when default_nettype is none
 201     - Fixed "wreduce" flipflop handling
 202     - Fixed FIRRTL to Verilog process instance subfield assignment
 203     - Added "write_verilog -siminit"
 204     - Several fixes and improvements for mem2reg memories
 205     - Fixed handling of task output ports in clocked always blocks
 206     - Improved handling of and-with-1 and or-with-0 in "opt_expr"
 207     - Added "read_aiger" frontend
 208     - Added "mutate" pass
 209     - Added "hdlname" attribute
 210     - Added "rename -output"
 211     - Added "read_ilang -lib"
 212     - Improved "proc" full_case detection and handling
 213     - Added "whitebox" and "lib_whitebox" attributes
 214     - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
 215     - Added Python bindings and support for Python plug-ins
 216     - Added "pmux2shiftx"
 217     - Added log_debug framework for reduced default verbosity
 218     - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
 219     - Added "peepopt" peephole optimisation pass using pmgen
 220     - Added approximate support for SystemVerilog "var" keyword
 221     - Added parsing of "specify" blocks into $specrule and $specify[23]
 222     - Added support for attributes on parameters and localparams
 223     - Added support for parsing attributes on port connections
 224     - Added "wreduce -keepdc"
 225     - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
 226     - Added Verilog wand/wor wire type support
 227     - Added support for elaboration system tasks
 228     - Added "muxcover -mux{4,8,16}=<cost>"
 229     - Added "muxcover -dmux=<cost>"
 230     - Added "muxcover -nopartial"
 231     - Added "muxpack" pass
 232     - Added "pmux2shiftx -norange"
 233     - Added support for "~" in filename parsing
 234     - Added "read_verilog -pwires" feature to turn parameters into wires
 235     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 236     - Fixed genvar to be a signed type
 237     - Added support for attributes on case rules
 238     - Added "upto" and "offset" to JSON frontend and backend
 239     - Several liberty file parser improvements
 240     - Fixed handling of more complex BRAM patterns
 241     - Add "write_aiger -I -O -B"
 242
 243  * Formal Verification
 244     - Added $changed support to read_verilog
 245     - Added "read_verilog -noassert -noassume -assert-assumes"
 246     - Added btor ops for $mul, $div, $mod and $concat
 247     - Added yosys-smtbmc support for btor witnesses
 248     - Added "supercover" pass
 249     - Fixed $global_clock handling vs autowire
 250     - Added $dffsr support to "async2sync"
 251     - Added "fmcombine" pass
 252     - Added memory init support in "write_btor"
 253     - Added "cutpoint" pass
 254     - Changed "ne" to "neq" in btor2 output
 255     - Added support for SVA "final" keyword
 256     - Added "fmcombine -initeq -anyeq"
 257     - Added timescale and generated-by header to yosys-smtbmc vcd output
 258     - Improved BTOR2 handling of undriven wires
 259
 260  * Verific support
 261     - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
 262     - Improved support for asymmetric memories
 263     - Added "verific -chparam"
 264     - Fixed "verific -extnets" for more complex situations
 265     - Added "read -verific" and "read -noverific"
 266     - Added "hierarchy -chparam"
 267
 268  * New back-ends
 269     - Added initial Anlogic support
 270     - Added initial SmartFusion2 and IGLOO2 support
 271
 272  * ECP5 support
 273     - Added "synth_ecp5 -nowidelut"
 274     - Added BRAM inference support to "synth_ecp5"
 275     - Added support for transforming Diamond IO and flipflop primitives
 276
 277  * iCE40 support
 278     - Added "ice40_unlut" pass
 279     - Added "synth_ice40 -relut"
 280     - Added "synth_ice40 -noabc"
 281     - Added "synth_ice40 -dffe_min_ce_use"
 282     - Added DSP inference support using pmgen
 283     - Added support for initialising BRAM primitives from a file
 284     - Added iCE40 Ultra RGB LED driver cells
 285
 286  * Xilinx support
 287     - Use "write_edif -pvector bra" for Xilinx EDIF files
 288     - Fixes for VPR place and route support with "synth_xilinx"
 289     - Added more cell simulation models
 290     - Added "synth_xilinx -family"
 291     - Added "stat -tech xilinx" to estimate logic cell usage
 292     - Added "synth_xilinx -nocarry"
 293     - Added "synth_xilinx -nowidelut"
 294     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 295     - Added support for mapping RAM32X1D
 296
 297 Yosys 0.7 .. Yosys 0.8
 298 ----------------------
 299
 300  * Various
 301     - Many bugfixes and small improvements
 302     - Strip debug symbols from installed binary
 303     - Replace -ignore_redef with -[no]overwrite in front-ends
 304     - Added write_verilog hex dump support, add -nohex option
 305     - Added "write_verilog -decimal"
 306     - Added "scc -set_attr"
 307     - Added "verilog_defines" command
 308     - Remember defines from one read_verilog to next
 309     - Added support for hierarchical defparam
 310     - Added FIRRTL back-end
 311     - Improved ABC default scripts
 312     - Added "design -reset-vlog"
 313     - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
 314     - Added Verilog $rtoi and $itor support
 315     - Added "check -initdrv"
 316     - Added "read_blif -wideports"
 317     - Added support for SystemVerilog "++" and "--" operators
 318     - Added support for SystemVerilog unique, unique0, and priority case
 319     - Added "write_edif" options for edif "flavors"
 320     - Added support for resetall compiler directive
 321     - Added simple C beck-end (bitwise combinatorical only atm)
 322     - Added $_ANDNOT_ and $_ORNOT_ cell types
 323     - Added cell library aliases to "abc -g"
 324     - Added "setundef -anyseq"
 325     - Added "chtype" command
 326     - Added "design -import"
 327     - Added "write_table" command
 328     - Added "read_json" command
 329     - Added "sim" command
 330     - Added "extract_fa" and "extract_reduce" commands
 331     - Added "extract_counter" command
 332     - Added "opt_demorgan" command
 333     - Added support for $size and $bits SystemVerilog functions
 334     - Added "blackbox" command
 335     - Added "ltp" command
 336     - Added support for editline as replacement for readline
 337     - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
 338     - Added "yosys -E" for creating Makefile dependencies files
 339     - Added "synth -noshare"
 340     - Added "memory_nordff"
 341     - Added "setundef -undef -expose -anyconst"
 342     - Added "expose -input"
 343     - Added specify/specparam parser support (simply ignore them)
 344     - Added "write_blif -inames -iattr"
 345     - Added "hierarchy -simcheck"
 346     - Added an option to statically link abc into yosys
 347     - Added protobuf back-end
 348     - Added BLIF parsing support for .conn and .cname
 349     - Added read_verilog error checking for reg/wire/logic misuse
 350     - Added "make coverage" and ENABLE_GCOV build option
 351
 352  * Changes in Yosys APIs
 353     - Added ConstEval defaultval feature
 354     - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
 355     - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
 356     - Added log_file_warning() and log_file_error() functions
 357
 358  * Formal Verification
 359     - Added "write_aiger"
 360     - Added "yosys-smtbmc --aig"
 361     - Added "always <positive_int>" to .smtc format
 362     - Added $cover cell type and support for cover properties
 363     - Added $fair/$live cell type and support for liveness properties
 364     - Added smtbmc support for memory vcd dumping
 365     - Added "chformal" command
 366     - Added "write_smt2 -stbv" and "write_smt2 -stdt"
 367     - Fix equiv_simple, old behavior now available with "equiv_simple -short"
 368     - Change to Yices2 as default SMT solver (it is GPL now)
 369     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
 370     - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
 371     - Added a brand new "write_btor" command for BTOR2
 372     - Added clk2fflogic memory support and other improvements
 373     - Added "async memory write" support to write_smt2
 374     - Simulate clock toggling in yosys-smtbmc VCD output
 375     - Added $allseq/$allconst cells for EA-solving
 376     - Make -nordff the default in "prep"
 377     - Added (* gclk *) attribute
 378     - Added "async2sync" pass for single-clock designs with async resets
 379
 380  * Verific support
 381     - Many improvements in Verific front-end
 382     - Added proper handling of concurent SVA properties
 383     - Map "const" and "rand const" to $anyseq/$anyconst
 384     - Added "verific -import -flatten" and "verific -import -extnets"
 385     - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
 386     - Remove PSL support (because PSL has been removed in upstream Verific)
 387     - Improve integration with "hierarchy" command design elaboration
 388     - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
 389     - Added simpilied "read" command that automatically uses verific if available
 390     - Added "verific -set-<severity> <msg_id>.."
 391     - Added "verific -work <libname>"
 392
 393  * New back-ends
 394     - Added initial Coolrunner-II support
 395     - Added initial eASIC support
 396     - Added initial ECP5 support
 397
 398  * GreenPAK Support
 399     - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
 400
 401  * iCE40 Support
 402     - Add "synth_ice40 -vpr"
 403     - Add "synth_ice40 -nodffe"
 404     - Add "synth_ice40 -json"
 405     - Add Support for UltraPlus cells
 406
 407  * MAX10 and Cyclone IV Support
 408     - Added initial version of metacommand "synth_intel".
 409     - Improved write_verilog command to produce VQM netlist for Quartus Prime.
 410     - Added support for MAX10 FPGA family synthesis.
 411     - Added support for Cyclone IV family synthesis.
 412     - Added example of implementation for DE2i-150 board.
 413     - Added example of implementation for MAX10 development kit.
 414     - Added LFSR example from Asic World.
 415     - Added "dffinit -highlow" for mapping to Intel primitives
 416
 417
 418 Yosys 0.6 .. Yosys 0.7
 419 ----------------------
 420
 421  * Various
 422     - Added "yosys -D" feature
 423     - Added support for installed plugins in $(DATDIR)/plugins/
 424     - Renamed opt_const to opt_expr
 425     - Renamed opt_share to opt_merge
 426     - Added "prep -flatten" and "synth -flatten"
 427     - Added "prep -auto-top" and "synth -auto-top"
 428     - Using "mfs" and "lutpack" in ABC lut mapping
 429     - Support for abstract modules in chparam
 430     - Cleanup abstract modules at end of "hierarchy -top"
 431     - Added tristate buffer support to iopadmap
 432     - Added opt_expr support for div/mod by power-of-two
 433     - Added "select -assert-min <N> -assert-max <N>"
 434     - Added "attrmvcp" pass
 435     - Added "attrmap" command
 436     - Added "tee +INT -INT"
 437     - Added "zinit" pass
 438     - Added "setparam -type"
 439     - Added "shregmap" pass
 440     - Added "setundef -init"
 441     - Added "nlutmap -assert"
 442     - Added $sop cell type and "abc -sop -I <num> -P <num>"
 443     - Added "dc2" to default ABC scripts
 444     - Added "deminout"
 445     - Added "insbuf" command
 446     - Added "prep -nomem"
 447     - Added "opt_rmdff -keepdc"
 448     - Added "prep -nokeepdc"
 449     - Added initial version of "synth_gowin"
 450     - Added "fsm_expand -full"
 451     - Added support for fsm_encoding="user"
 452     - Many improvements in GreenPAK4 support
 453     - Added black box modules for all Xilinx 7-series lib cells
 454     - Added synth_ice40 support for latches via logic loops
 455     - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
 456
 457  * Build System
 458     - Added ABCEXTERNAL and ABCURL make variables
 459     - Added BINDIR, LIBDIR, and DATDIR make variables
 460     - Added PKG_CONFIG make variable
 461     - Added SEED make variable (for "make test")
 462     - Added YOSYS_VER_STR make variable
 463     - Updated min GCC requirement to GCC 4.8
 464     - Updated required Bison version to Bison 3.x
 465
 466  * Internal APIs
 467     - Added ast.h to exported headers
 468     - Added ScriptPass helper class for script-like passes
 469     - Added CellEdgesDatabase API
 470
 471  * Front-ends and Back-ends
 472     - Added filename glob support to all front-ends
 473     - Added avail (black-box) module params to ilang format
 474     - Added $display %m support
 475     - Added support for $stop Verilog system task
 476     - Added support for SystemVerilog packages
 477     - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
 478     - Added support for "active high" and "active low" latches in read_blif and write_blif
 479     - Use init value "2" for all uninitialized FFs in BLIF back-end
 480     - Added "read_blif -sop"
 481     - Added "write_blif -noalias"
 482     - Added various write_blif options for VTR support
 483     - write_json: also write module attributes.
 484     - Added "write_verilog -nodec -nostr -defparam"
 485     - Added "read_verilog -norestrict -assume-asserts"
 486     - Added support for bus interfaces to "read_liberty -lib"
 487     - Added liberty parser support for types within cell decls
 488     - Added "write_verilog -renameprefix -v"
 489     - Added "write_edif -nogndvcc"
 490
 491  * Formal Verification
 492     - Support for hierarchical designs in smt2 back-end
 493     - Yosys-smtbmc: Support for hierarchical VCD dumping
 494     - Added $initstate cell type and vlog function
 495     - Added $anyconst and $anyseq cell types and vlog functions
 496     - Added printing of code loc of failed asserts to yosys-smtbmc
 497     - Added memory_memx pass, "memory -memx", and "prep -memx"
 498     - Added "proc_mux -ifx"
 499     - Added "yosys-smtbmc -g"
 500     - Deprecated "write_smt2 -regs" (by default on now)
 501     - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
 502     - Added support for memories to smtio.py
 503     - Added "yosys-smtbmc --dump-vlogtb"
 504     - Added "yosys-smtbmc --smtc --dump-smtc"
 505     - Added "yosys-smtbmc --dump-all"
 506     - Added assertpmux command
 507     - Added "yosys-smtbmc --unroll"
 508     - Added $past, $stable, $rose, $fell SVA functions
 509     - Added "yosys-smtbmc --noinfo and --dummy"
 510     - Added "yosys-smtbmc --noincr"
 511     - Added "yosys-smtbmc --cex <filename>"
 512     - Added $ff and $_FF_ cell types
 513     - Added $global_clock verilog syntax support for creating $ff cells
 514     - Added clk2fflogic
 515
 516
 517 Yosys 0.5 .. Yosys 0.6
 518 ----------------------
 519
 520  * Various
 521      - Added Contributor Covenant Code of Conduct
 522      - Various improvements in dict<> and pool<>
 523      - Added hashlib::mfp and refactored SigMap
 524      - Improved support for reals as module parameters
 525      - Various improvements in SMT2 back-end
 526      - Added "keep_hierarchy" attribute
 527      - Verilog front-end: define `BLACKBOX in -lib mode
 528      - Added API for converting internal cells to AIGs
 529      - Added ENABLE_LIBYOSYS Makefile option
 530      - Removed "techmap -share_map" (use "-map +/filename" instead)
 531      - Switched all Python scripts to Python 3
 532      - Added support for $display()/$write() and $finish() to Verilog front-end
 533      - Added "yosys-smtbmc" formal verification flow
 534      - Added options for clang sanitizers to Makefile
 535
 536  * New commands and options
 537      - Added "scc -expect <N> -nofeedback"
 538      - Added "proc_dlatch"
 539      - Added "check"
 540      - Added "select %xe %cie %coe %M %C %R"
 541      - Added "sat -dump_json" (WaveJSON format)
 542      - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
 543      - Added "sat -stepsize" and "sat -tempinduct-step"
 544      - Added "sat -show-regs -show-public -show-all"
 545      - Added "write_json" (Native Yosys JSON format)
 546      - Added "write_blif -attr"
 547      - Added "dffinit"
 548      - Added "chparam"
 549      - Added "muxcover"
 550      - Added "pmuxtree"
 551      - Added memory_bram "make_outreg" feature
 552      - Added "splice -wires"
 553      - Added "dff2dffe -direct-match"
 554      - Added simplemap $lut support
 555      - Added "read_blif"
 556      - Added "opt_share -share_all"
 557      - Added "aigmap"
 558      - Added "write_smt2 -mem -regs -wires"
 559      - Added "memory -nordff"
 560      - Added "write_smv"
 561      - Added "synth -nordff -noalumacc"
 562      - Added "rename -top new_name"
 563      - Added "opt_const -clkinv"
 564      - Added "synth -nofsm"
 565      - Added "miter -assert"
 566      - Added "read_verilog -noautowire"
 567      - Added "read_verilog -nodpi"
 568      - Added "tribuf"
 569      - Added "lut2mux"
 570      - Added "nlutmap"
 571      - Added "qwp"
 572      - Added "test_cell -noeval"
 573      - Added "edgetypes"
 574      - Added "equiv_struct"
 575      - Added "equiv_purge"
 576      - Added "equiv_mark"
 577      - Added "equiv_add -try -cell"
 578      - Added "singleton"
 579      - Added "abc -g -luts"
 580      - Added "torder"
 581      - Added "write_blif -cname"
 582      - Added "submod -copy"
 583      - Added "dffsr2dff"
 584      - Added "stat -liberty"
 585
 586  * Synthesis metacommands
 587      - Various improvements in synth_xilinx
 588      - Added synth_ice40 and synth_greenpak4
 589      - Added "prep" metacommand for "synthesis lite"
 590
 591  * Cell library changes
 592      - Added cell types to "help" system
 593      - Added $meminit cell type
 594      - Added $assume cell type
 595      - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
 596      - Added $tribuf and $_TBUF_ cell types
 597      - Added read-enable to memory model
 598
 599  * YosysJS
 600      - Various improvements in emscripten build
 601      - Added alternative webworker-based JS API
 602      - Added a few example applications
 603
 604
 605 Yosys 0.4 .. Yosys 0.5
 606 ----------------------
 607
 608  * API changes
 609      - Added log_warning()
 610      - Added eval_select_args() and eval_select_op()
 611      - Added cell->known(), cell->input(portname), cell->output(portname)
 612      - Skip blackbox modules in design->selected_modules()
 613      - Replaced std::map<> and std::set<> with dict<> and pool<>
 614      - New SigSpec::extend() is what used to be SigSpec::extend_u0()
 615      - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
 616
 617  * Cell library changes
 618      - Added flip-flops with enable ($dffe etc.)
 619      - Added $equiv cells for equivalence checking framework
 620
 621  * Various
 622      - Updated ABC to hg rev 61ad5f908c03
 623      - Added clock domain partitioning to ABC pass
 624      - Improved plugin building (see "yosys-config --build")
 625      - Added ENABLE_NDEBUG Makefile flag for high-performance builds
 626      - Added "yosys -d", "yosys -L" and other driver improvements
 627      - Added support for multi-bit (array) cell ports to "write_edif"
 628      - Now printing most output to stdout, not stderr
 629      - Added "onehot" attribute (set by "fsm_map")
 630      - Various performance improvements
 631      - Vastly improved Xilinx flow
 632      - Added "make unsintall"
 633
 634  * Equivalence checking
 635      - Added equivalence checking commands:
 636          equiv_make equiv_simple equiv_status
 637          equiv_induct equiv_miter
 638          equiv_add equiv_remove
 639
 640  * Block RAM support:
 641      - Added "memory_bram" command
 642      - Added BRAM support to Xilinx flow
 643
 644  * Other New Commands and Options
 645      - Added "dff2dffe"
 646      - Added "fsm -encfile"
 647      - Added "dfflibmap -prepare"
 648      - Added "write_blid -unbuf -undef -blackbox"
 649      - Added "write_smt2" for writing SMT-LIBv2 files
 650      - Added "test_cell -w -muxdiv"
 651      - Added "select -read"
 652
 653
 654 Yosys 0.3.0 .. Yosys 0.4
 655 ------------------------
 656
 657  * Platform Support
 658      - Added support for mxe-based cross-builds for win32
 659      - Added sourcecode-export as VisualStudio project
 660      - Added experimental EMCC (JavaScript) support
 661
 662  * Verilog Frontend
 663      - Added -sv option for SystemVerilog (and automatic *.sv file support)
 664      - Added support for real-valued constants and constant expressions
 665      - Added support for non-standard "via_celltype" attribute on task/func
 666      - Added support for non-standard "module mod_name(...);" syntax
 667      - Added support for non-standard """ macro bodies
 668      - Added support for array with more than one dimension
 669      - Added support for $readmemh and $readmemb
 670      - Added support for DPI functions
 671
 672  * Changes in internal cell library
 673      - Added $shift and $shiftx cell types
 674      - Added $alu, $lcu, $fa and $macc cell types
 675      - Removed $bu0 and $safe_pmux cell types
 676      - $mem/$memwr WR_EN input is now a per-data-bit enable signal
 677      - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
 678      - Renamed ports of $lut cells (from I->O to A->Y)
 679      - Renamed $_INV_ to $_NOT_
 680
 681  * Changes for simple synthesis flows
 682      - There is now a "synth" command with a recommended default script
 683      - Many improvements in synthesis of arithmetic functions to gates
 684          - Multipliers and adders with many operands are using carry-save adder trees
 685          - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
 686      - Various new high-level optimizations on RTL netlist
 687      - Various improvements in FSM optimization
 688      - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
 689
 690  * Changes in internal APIs and RTLIL
 691      - Added log_id() and log_cell() helper functions
 692      - Added function-like cell creation helpers
 693      - Added GetSize() function (like .size() but with int)
 694      - Major refactoring of RTLIL::Module and related classes
 695      - Major refactoring of RTLIL::SigSpec and related classes
 696      - Now RTLIL::IdString is essentially an int
 697      - Added macros for code coverage counters
 698      - Added some Makefile magic for pretty make logs
 699      - Added "kernel/yosys.h" with all the core definitions
 700      - Changed a lot of code from FILE* to c++ streams
 701      - Added RTLIL::Monitor API and "trace" command
 702      - Added "Yosys" C++ namespace
 703
 704  * Changes relevant to SAT solving
 705      - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
 706      - Added native ezSAT support for vector shift ops
 707      - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
 708
 709  * New commands (or large improvements to commands)
 710      - Added "synth" command with default script
 711      - Added "share" (finally some real resource sharing)
 712      - Added "memory_share" (reduce number of ports on memories)
 713      - Added "wreduce" and "alumacc" commands
 714      - Added "opt -keepdc -fine -full -fast"
 715      - Added some "test_*" commands
 716
 717  * Various other changes
 718      - Added %D and %c select operators
 719      - Added support for labels in yosys scripts
 720      - Added support for here-documents in yosys scripts
 721      - Support "+/" prefix for files from proc_share_dir
 722      - Added "autoidx" statement to ilang language
 723      - Switched from "yosys-svgviewer" to "xdot"
 724      - Renamed "stdcells.v" to "techmap.v"
 725      - Various bug fixes and small improvements
 726      - Improved welcome and bye messages
 727
 728
 729 Yosys 0.2.0 .. Yosys 0.3.0
 730 --------------------------
 731
 732  * Driver program and overall behavior:
 733      - Added "design -push" and "design -pop"
 734      - Added "tee" command for redirecting log output
 735
 736  * Changes in the internal cell library:
 737      - Added $dlatchsr and $_DLATCHSR_???_ cell types
 738
 739  * Improvements in Verilog frontend:
 740      - Improved support for const functions (case, always, repeat)
 741      - The generate..endgenerate keywords are now optional
 742      - Added support for arrays of module instances
 743      - Added support for "`default_nettype" directive
 744      - Added support for "`line" directive
 745
 746  * Other front- and back-ends:
 747      - Various changes to "write_blif" options
 748      - Various improvements in EDIF backend
 749      - Added "vhdl2verilog" pseudo-front-end
 750      - Added "verific" pseudo-front-end
 751
 752  * Improvements in technology mapping:
 753      - Added support for recursive techmap
 754      - Added CONSTMSK and CONSTVAL features to techmap
 755      - Added _TECHMAP_CONNMAP_*_ feature to techmap
 756      - Added _TECHMAP_REPLACE_ feature to techmap
 757      - Added "connwrappers" command for wrap-extract-unwrap method
 758      - Added "extract -map %<design_name>" feature
 759      - Added "extract -ignore_param ..." and "extract -ignore_parameters"
 760      - Added "techmap -max_iter" option
 761
 762  * Improvements to "eval" and "sat" framework:
 763      - Now include a copy of Minisat (with build fixes applied)
 764      - Switched to Minisat::SimpSolver as SAT back-end
 765      - Added "sat -dump_vcd" feature
 766      - Added "sat -dump_cnf" feature
 767      - Added "sat -initsteps <N>" feature
 768      - Added "freduce -stop <N>" feature
 769      - Added "freduce -dump <prefix>" feature
 770
 771  * Integration with ABC:
 772      - Updated ABC rev to 7600ffb9340c
 773
 774  * Improvements in the internal APIs:
 775      - Added RTLIL::Module::add... helper methods
 776      - Various build fixes for OSX (Darwin) and OpenBSD
 777
 778
 779 Yosys 0.1.0 .. Yosys 0.2.0
 780 --------------------------
 781
 782  * Changes to the driver program:
 783      - Added "yosys -h" and "yosys -H"
 784      - Added support for backslash line continuation in scripts
 785      - Added support for #-comments in same line as command
 786      - Added "echo" and "log" commands
 787
 788  * Improvements in Verilog frontend:
 789      - Added support for local registers in named blocks
 790      - Added support for "case" in "generate" blocks
 791      - Added support for $clog2 system function
 792      - Added support for basic SystemVerilog assert statements
 793      - Added preprocessor support for macro arguments
 794      - Added preprocessor support for `elsif statement
 795      - Added "verilog_defaults" command
 796      - Added read_verilog -icells option
 797      - Added support for constant sizes from parameters
 798      - Added "read_verilog -setattr"
 799      - Added support for function returning 'integer'
 800      - Added limited support for function calls in parameter values
 801      - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
 802
 803  * Other front- and back-ends:
 804      - Added BTOR backend
 805      - Added Liberty frontend
 806
 807  * Improvements in technology mapping:
 808      - The "dfflibmap" command now strongly prefers solutions with
 809            no inverters in clock paths
 810      - The "dfflibmap" command now prefers cells with smaller area
 811      - Added support for multiple -map options to techmap
 812      - Added "dfflibmap" support for //-comments in liberty files
 813      - Added "memory_unpack" command to revert "memory_collect"
 814      - Added standard techmap rule "techmap -share_map pmux2mux.v"
 815      - Added "iopadmap -bits"
 816      - Added "setundef" command
 817      - Added "hilomap" command
 818
 819  * Changes in the internal cell library:
 820      - Major rewrite of simlib.v for better compatibility with other tools
 821      - Added PRIORITY parameter to $memwr cells
 822      - Added TRANSPARENT parameter to $memrd cells
 823      - Added RD_TRANSPARENT parameter to $mem cells
 824      - Added $bu0 cell (always 0-extend, even undef MSB)
 825      - Added $assert cell type
 826      - Added $slice and $concat cell types
 827
 828  * Integration with ABC:
 829      - Updated ABC to hg rev 2058c8ccea68
 830      - Tighter integration of ABC build with Yosys build. The make
 831            targets 'make abc' and 'make install-abc' are now obsolete.
 832      - Added support for passing FFs from one clock domain through ABC
 833      - Now always use BLIF as exchange format with ABC
 834      - Added support for "abc -script +<command_sequence>"
 835      - Improved standard ABC recipe
 836      - Added support for "keep" attribute to abc command
 837      - Added "abc -dff / -clk / -keepff" options
 838
 839  * Improvements to "eval" and "sat" framework:
 840      - Added support for "0" and "~0" in right-hand side -set expressions
 841      - Added "eval -set-undef" and "eval -table"
 842      - Added "sat -set-init" and "sat -set-init-*" for sequential problems
 843      - Added undef support to SAT solver, incl. various new "sat" options
 844      - Added correct support for === and !== for "eval" and "sat"
 845      - Added "sat -tempinduct" (default -seq is now non-induction sequential)
 846      - Added "sat -prove-asserts"
 847      - Complete rewrite of the 'freduce' command
 848      - Added "miter" command
 849      - Added "sat -show-inputs" and "sat -show-outputs"
 850      - Added "sat -ignore_unknown_cells" (now produce an error by default)
 851      - Added "sat -falsify"
 852      - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
 853      - Added "expose" command
 854      - Added support for @<sel_name> to sat and eval signal expressions
 855
 856  * Changes in the 'make test' framework and auxiliary test tools:
 857      - Added autotest.sh -p and -f options
 858      - Replaced autotest.sh ISIM support with XSIM support
 859      - Added test cases for SAT framework
 860
 861  * Added "abbreviated IDs":
 862      - Now $<something>$foo can be abbreviated as $foo.
 863      - Usually this last part is a unique id (from RTLIL::autoidx)
 864      - This abbreviated IDs are now also used in "show" output
 865
 866  * Other changes to selection framework:
 867      - Now */ is optional in */<mode>:<arg> expressions
 868      - Added "select -assert-none" and "select -assert-any"
 869      - Added support for matching modules by attribute (A:<expr>)
 870      - Added "select -none"
 871      - Added support for r:<expr> pattern for matching cell parameters
 872      - Added support for !=, <, <=, >=, > for attribute and parameter matching
 873      - Added support for %s for selecting sub-modules
 874      - Added support for %m for expanding selections to whole modules
 875      - Added support for i:*, o:* and x:* pattern for selecting module ports
 876      - Added support for s:<expr> pattern for matching wire width
 877      - Added support for %a operation to select wire aliases
 878
 879  * Various other changes to commands and options:
 880      - The "ls" command now supports wildcards
 881      - Added "show -pause" and "show -format dot"
 882      - Added "show -color" support for cells
 883      - Added "show -label" and "show -notitle"
 884      - Added "dump -m" and "dump -n"
 885      - Added "history" command
 886      - Added "rename -hide"
 887      - Added "connect" command
 888      - Added "splitnets -driver"
 889      - Added "opt_const -mux_undef"
 890      - Added "opt_const -mux_bool"
 891      - Added "opt_const -undriven"
 892      - Added "opt -mux_undef -mux_bool -undriven -purge"
 893      - Added "hierarchy -libdir"
 894      - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
 895      - Added "delete" command
 896      - Added "dump -append"
 897      - Added "setattr" and "setparam" commands
 898      - Added "design -stash/-copy-from/-copy-to"
 899      - Added "copy" command
 900      - Added "splice" command
 901