CHANGELOG

   1
   2 List of major changes and improvements between releases
   3 =======================================================
   4
   5
   6 Yosys 0.9 .. Yosys 0.9-dev
   7 --------------------------
   8
   9  * Various
  10     - Added "write_xaiger" backend
  11     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
  12     - Added "synth_xilinx -abc9" (experimental)
  13     - Added "synth_ice40 -abc9" (experimental)
  14     - Added "synth -abc9" (experimental)
  15     - Added "script -scriptwire"
  16     - Added "synth_xilinx -nocarry"
  17     - Added "synth_xilinx -nowidelut"
  18     - Added "synth_ecp5 -nowidelut"
  19     - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
  20     - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
  21     - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
  22     - Renamed labels in synth_intel (e.g. bram -> map_bram)
  23     - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
  24     - Added automatic gzip decompression for frontends
  25     - Added $_NMUX_ cell type
  26     - Added automatic gzip compression (based on filename extension) for backends
  27     - Improve attribute and parameter encoding in JSON to avoid ambiguities between
  28       bit vectors and strings containing [01xz]*
  29     - Added "clkbufmap" pass
  30     - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
  31     - Added "synth_xilinx -ise" (experimental)
  32     - Added "synth_xilinx -iopad"
  33     - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
  34     - Improvements in pmgen: subpattern and recursive matches
  35     - Added "opt_share" pass, run as part of "opt -full"
  36     - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
  37     - Removed "ice40_unlut"
  38     - Improvements in pmgen: slices, choices, define, generate
  39     - Added "xilinx_srl" for Xilinx shift register extraction
  40     - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
  41     - Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
  42     - Added "-match-init" option to "dff2dffs" pass
  43     - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
  44     - Added "ice40_dsp" for Lattice iCE40 DSP packing
  45     - Added "xilinx_dsp" for Xilinx DSP packing
  46     - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
  47     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
  48     - "synth_ice40 -dsp" to infer DSP blocks
  49
  50 Yosys 0.8 .. Yosys 0.9
  51 ----------------------
  52
  53  * Various
  54     - Many bugfixes and small improvements
  55     - Added support for SystemVerilog interfaces and modports
  56     - Added "write_edif -attrprop"
  57     - Added "opt_lut" pass
  58     - Added "gate2lut.v" techmap rule
  59     - Added "rename -src"
  60     - Added "equiv_opt" pass
  61     - Added "flowmap" LUT mapping pass
  62     - Added "rename -wire" to rename cells based on the wires they drive
  63     - Added "bugpoint" for creating minimised testcases
  64     - Added "write_edif -gndvccy"
  65     - "write_verilog" to escape Verilog keywords
  66     - Fixed sign handling of real constants
  67     - "write_verilog" to write initial statement for initial flop state
  68     - Added pmgen pattern matcher generator
  69     - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
  70     - Added "setundef -params" to replace undefined cell parameters
  71     - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
  72     - Fixed handling of defparam when default_nettype is none
  73     - Fixed "wreduce" flipflop handling
  74     - Fixed FIRRTL to Verilog process instance subfield assignment
  75     - Added "write_verilog -siminit"
  76     - Several fixes and improvements for mem2reg memories
  77     - Fixed handling of task output ports in clocked always blocks
  78     - Improved handling of and-with-1 and or-with-0 in "opt_expr"
  79     - Added "read_aiger" frontend
  80     - Added "mutate" pass
  81     - Added "hdlname" attribute
  82     - Added "rename -output"
  83     - Added "read_ilang -lib"
  84     - Improved "proc" full_case detection and handling
  85     - Added "whitebox" and "lib_whitebox" attributes
  86     - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
  87     - Added Python bindings and support for Python plug-ins
  88     - Added "pmux2shiftx"
  89     - Added log_debug framework for reduced default verbosity
  90     - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
  91     - Added "peepopt" peephole optimisation pass using pmgen
  92     - Added approximate support for SystemVerilog "var" keyword
  93     - Added parsing of "specify" blocks into $specrule and $specify[23]
  94     - Added support for attributes on parameters and localparams
  95     - Added support for parsing attributes on port connections
  96     - Added "wreduce -keepdc"
  97     - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
  98     - Added Verilog wand/wor wire type support
  99     - Added support for elaboration system tasks
 100     - Added "muxcover -mux{4,8,16}=<cost>"
 101     - Added "muxcover -dmux=<cost>"
 102     - Added "muxcover -nopartial"
 103     - Added "muxpack" pass
 104     - Added "pmux2shiftx -norange"
 105     - Added support for "~" in filename parsing
 106     - Added "read_verilog -pwires" feature to turn parameters into wires
 107     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 108     - Fixed genvar to be a signed type
 109     - Added support for attributes on case rules
 110     - Added "upto" and "offset" to JSON frontend and backend
 111     - Several liberty file parser improvements
 112     - Fixed handling of more complex BRAM patterns
 113     - Add "write_aiger -I -O -B"
 114
 115  * Formal Verification
 116     - Added $changed support to read_verilog
 117     - Added "read_verilog -noassert -noassume -assert-assumes"
 118     - Added btor ops for $mul, $div, $mod and $concat
 119     - Added yosys-smtbmc support for btor witnesses
 120     - Added "supercover" pass
 121     - Fixed $global_clock handling vs autowire
 122     - Added $dffsr support to "async2sync"
 123     - Added "fmcombine" pass
 124     - Added memory init support in "write_btor"
 125     - Added "cutpoint" pass
 126     - Changed "ne" to "neq" in btor2 output
 127     - Added support for SVA "final" keyword
 128     - Added "fmcombine -initeq -anyeq"
 129     - Added timescale and generated-by header to yosys-smtbmc vcd output
 130     - Improved BTOR2 handling of undriven wires
 131
 132  * Verific support
 133     - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
 134     - Improved support for asymmetric memories
 135     - Added "verific -chparam"
 136     - Fixed "verific -extnets" for more complex situations
 137     - Added "read -verific" and "read -noverific"
 138     - Added "hierarchy -chparam"
 139
 140  * New back-ends
 141     - Added initial Anlogic support
 142     - Added initial SmartFusion2 and IGLOO2 support
 143
 144  * ECP5 support
 145     - Added "synth_ecp5 -nowidelut"
 146     - Added BRAM inference support to "synth_ecp5"
 147     - Added support for transforming Diamond IO and flipflop primitives
 148
 149  * iCE40 support
 150     - Added "ice40_unlut" pass
 151     - Added "synth_ice40 -relut"
 152     - Added "synth_ice40 -noabc"
 153     - Added "synth_ice40 -dffe_min_ce_use"
 154     - Added DSP inference support using pmgen
 155     - Added support for initialising BRAM primitives from a file
 156     - Added iCE40 Ultra RGB LED driver cells
 157
 158  * Xilinx support
 159     - Use "write_edif -pvector bra" for Xilinx EDIF files
 160     - Fixes for VPR place and route support with "synth_xilinx"
 161     - Added more cell simulation models
 162     - Added "synth_xilinx -family"
 163     - Added "stat -tech xilinx" to estimate logic cell usage
 164     - Added "synth_xilinx -nocarry"
 165     - Added "synth_xilinx -nowidelut"
 166     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 167     - Added support for mapping RAM32X1D
 168
 169 Yosys 0.7 .. Yosys 0.8
 170 ----------------------
 171
 172  * Various
 173     - Many bugfixes and small improvements
 174     - Strip debug symbols from installed binary
 175     - Replace -ignore_redef with -[no]overwrite in front-ends
 176     - Added write_verilog hex dump support, add -nohex option
 177     - Added "write_verilog -decimal"
 178     - Added "scc -set_attr"
 179     - Added "verilog_defines" command
 180     - Remember defines from one read_verilog to next
 181     - Added support for hierarchical defparam
 182     - Added FIRRTL back-end
 183     - Improved ABC default scripts
 184     - Added "design -reset-vlog"
 185     - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
 186     - Added Verilog $rtoi and $itor support
 187     - Added "check -initdrv"
 188     - Added "read_blif -wideports"
 189     - Added support for SystemVerilog "++" and "--" operators
 190     - Added support for SystemVerilog unique, unique0, and priority case
 191     - Added "write_edif" options for edif "flavors"
 192     - Added support for resetall compiler directive
 193     - Added simple C beck-end (bitwise combinatorical only atm)
 194     - Added $_ANDNOT_ and $_ORNOT_ cell types
 195     - Added cell library aliases to "abc -g"
 196     - Added "setundef -anyseq"
 197     - Added "chtype" command
 198     - Added "design -import"
 199     - Added "write_table" command
 200     - Added "read_json" command
 201     - Added "sim" command
 202     - Added "extract_fa" and "extract_reduce" commands
 203     - Added "extract_counter" command
 204     - Added "opt_demorgan" command
 205     - Added support for $size and $bits SystemVerilog functions
 206     - Added "blackbox" command
 207     - Added "ltp" command
 208     - Added support for editline as replacement for readline
 209     - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
 210     - Added "yosys -E" for creating Makefile dependencies files
 211     - Added "synth -noshare"
 212     - Added "memory_nordff"
 213     - Added "setundef -undef -expose -anyconst"
 214     - Added "expose -input"
 215     - Added specify/specparam parser support (simply ignore them)
 216     - Added "write_blif -inames -iattr"
 217     - Added "hierarchy -simcheck"
 218     - Added an option to statically link abc into yosys
 219     - Added protobuf back-end
 220     - Added BLIF parsing support for .conn and .cname
 221     - Added read_verilog error checking for reg/wire/logic misuse
 222     - Added "make coverage" and ENABLE_GCOV build option
 223
 224  * Changes in Yosys APIs
 225     - Added ConstEval defaultval feature
 226     - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
 227     - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
 228     - Added log_file_warning() and log_file_error() functions
 229
 230  * Formal Verification
 231     - Added "write_aiger"
 232     - Added "yosys-smtbmc --aig"
 233     - Added "always <positive_int>" to .smtc format
 234     - Added $cover cell type and support for cover properties
 235     - Added $fair/$live cell type and support for liveness properties
 236     - Added smtbmc support for memory vcd dumping
 237     - Added "chformal" command
 238     - Added "write_smt2 -stbv" and "write_smt2 -stdt"
 239     - Fix equiv_simple, old behavior now available with "equiv_simple -short"
 240     - Change to Yices2 as default SMT solver (it is GPL now)
 241     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
 242     - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
 243     - Added a brand new "write_btor" command for BTOR2
 244     - Added clk2fflogic memory support and other improvements
 245     - Added "async memory write" support to write_smt2
 246     - Simulate clock toggling in yosys-smtbmc VCD output
 247     - Added $allseq/$allconst cells for EA-solving
 248     - Make -nordff the default in "prep"
 249     - Added (* gclk *) attribute
 250     - Added "async2sync" pass for single-clock designs with async resets
 251
 252  * Verific support
 253     - Many improvements in Verific front-end
 254     - Added proper handling of concurent SVA properties
 255     - Map "const" and "rand const" to $anyseq/$anyconst
 256     - Added "verific -import -flatten" and "verific -import -extnets"
 257     - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
 258     - Remove PSL support (because PSL has been removed in upstream Verific)
 259     - Improve integration with "hierarchy" command design elaboration
 260     - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
 261     - Added simpilied "read" command that automatically uses verific if available
 262     - Added "verific -set-<severity> <msg_id>.."
 263     - Added "verific -work <libname>"
 264
 265  * New back-ends
 266     - Added initial Coolrunner-II support
 267     - Added initial eASIC support
 268     - Added initial ECP5 support
 269
 270  * GreenPAK Support
 271     - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
 272
 273  * iCE40 Support
 274     - Add "synth_ice40 -vpr"
 275     - Add "synth_ice40 -nodffe"
 276     - Add "synth_ice40 -json"
 277     - Add Support for UltraPlus cells
 278
 279  * MAX10 and Cyclone IV Support
 280     - Added initial version of metacommand "synth_intel".
 281     - Improved write_verilog command to produce VQM netlist for Quartus Prime.
 282     - Added support for MAX10 FPGA family synthesis.
 283     - Added support for Cyclone IV family synthesis.
 284     - Added example of implementation for DE2i-150 board.
 285     - Added example of implementation for MAX10 development kit.
 286     - Added LFSR example from Asic World.
 287     - Added "dffinit -highlow" for mapping to Intel primitives
 288
 289
 290 Yosys 0.6 .. Yosys 0.7
 291 ----------------------
 292
 293  * Various
 294     - Added "yosys -D" feature
 295     - Added support for installed plugins in $(DATDIR)/plugins/
 296     - Renamed opt_const to opt_expr
 297     - Renamed opt_share to opt_merge
 298     - Added "prep -flatten" and "synth -flatten"
 299     - Added "prep -auto-top" and "synth -auto-top"
 300     - Using "mfs" and "lutpack" in ABC lut mapping
 301     - Support for abstract modules in chparam
 302     - Cleanup abstract modules at end of "hierarchy -top"
 303     - Added tristate buffer support to iopadmap
 304     - Added opt_expr support for div/mod by power-of-two
 305     - Added "select -assert-min <N> -assert-max <N>"
 306     - Added "attrmvcp" pass
 307     - Added "attrmap" command
 308     - Added "tee +INT -INT"
 309     - Added "zinit" pass
 310     - Added "setparam -type"
 311     - Added "shregmap" pass
 312     - Added "setundef -init"
 313     - Added "nlutmap -assert"
 314     - Added $sop cell type and "abc -sop -I <num> -P <num>"
 315     - Added "dc2" to default ABC scripts
 316     - Added "deminout"
 317     - Added "insbuf" command
 318     - Added "prep -nomem"
 319     - Added "opt_rmdff -keepdc"
 320     - Added "prep -nokeepdc"
 321     - Added initial version of "synth_gowin"
 322     - Added "fsm_expand -full"
 323     - Added support for fsm_encoding="user"
 324     - Many improvements in GreenPAK4 support
 325     - Added black box modules for all Xilinx 7-series lib cells
 326     - Added synth_ice40 support for latches via logic loops
 327     - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
 328
 329  * Build System
 330     - Added ABCEXTERNAL and ABCURL make variables
 331     - Added BINDIR, LIBDIR, and DATDIR make variables
 332     - Added PKG_CONFIG make variable
 333     - Added SEED make variable (for "make test")
 334     - Added YOSYS_VER_STR make variable
 335     - Updated min GCC requirement to GCC 4.8
 336     - Updated required Bison version to Bison 3.x
 337
 338  * Internal APIs
 339     - Added ast.h to exported headers
 340     - Added ScriptPass helper class for script-like passes
 341     - Added CellEdgesDatabase API
 342
 343  * Front-ends and Back-ends
 344     - Added filename glob support to all front-ends
 345     - Added avail (black-box) module params to ilang format
 346     - Added $display %m support
 347     - Added support for $stop Verilog system task
 348     - Added support for SystemVerilog packages
 349     - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
 350     - Added support for "active high" and "active low" latches in read_blif and write_blif
 351     - Use init value "2" for all uninitialized FFs in BLIF back-end
 352     - Added "read_blif -sop"
 353     - Added "write_blif -noalias"
 354     - Added various write_blif options for VTR support
 355     - write_json: also write module attributes.
 356     - Added "write_verilog -nodec -nostr -defparam"
 357     - Added "read_verilog -norestrict -assume-asserts"
 358     - Added support for bus interfaces to "read_liberty -lib"
 359     - Added liberty parser support for types within cell decls
 360     - Added "write_verilog -renameprefix -v"
 361     - Added "write_edif -nogndvcc"
 362
 363  * Formal Verification
 364     - Support for hierarchical designs in smt2 back-end
 365     - Yosys-smtbmc: Support for hierarchical VCD dumping
 366     - Added $initstate cell type and vlog function
 367     - Added $anyconst and $anyseq cell types and vlog functions
 368     - Added printing of code loc of failed asserts to yosys-smtbmc
 369     - Added memory_memx pass, "memory -memx", and "prep -memx"
 370     - Added "proc_mux -ifx"
 371     - Added "yosys-smtbmc -g"
 372     - Deprecated "write_smt2 -regs" (by default on now)
 373     - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
 374     - Added support for memories to smtio.py
 375     - Added "yosys-smtbmc --dump-vlogtb"
 376     - Added "yosys-smtbmc --smtc --dump-smtc"
 377     - Added "yosys-smtbmc --dump-all"
 378     - Added assertpmux command
 379     - Added "yosys-smtbmc --unroll"
 380     - Added $past, $stable, $rose, $fell SVA functions
 381     - Added "yosys-smtbmc --noinfo and --dummy"
 382     - Added "yosys-smtbmc --noincr"
 383     - Added "yosys-smtbmc --cex <filename>"
 384     - Added $ff and $_FF_ cell types
 385     - Added $global_clock verilog syntax support for creating $ff cells
 386     - Added clk2fflogic
 387
 388
 389 Yosys 0.5 .. Yosys 0.6
 390 ----------------------
 391
 392  * Various
 393      - Added Contributor Covenant Code of Conduct
 394      - Various improvements in dict<> and pool<>
 395      - Added hashlib::mfp and refactored SigMap
 396      - Improved support for reals as module parameters
 397      - Various improvements in SMT2 back-end
 398      - Added "keep_hierarchy" attribute
 399      - Verilog front-end: define `BLACKBOX in -lib mode
 400      - Added API for converting internal cells to AIGs
 401      - Added ENABLE_LIBYOSYS Makefile option
 402      - Removed "techmap -share_map" (use "-map +/filename" instead)
 403      - Switched all Python scripts to Python 3
 404      - Added support for $display()/$write() and $finish() to Verilog front-end
 405      - Added "yosys-smtbmc" formal verification flow
 406      - Added options for clang sanitizers to Makefile
 407
 408  * New commands and options
 409      - Added "scc -expect <N> -nofeedback"
 410      - Added "proc_dlatch"
 411      - Added "check"
 412      - Added "select %xe %cie %coe %M %C %R"
 413      - Added "sat -dump_json" (WaveJSON format)
 414      - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
 415      - Added "sat -stepsize" and "sat -tempinduct-step"
 416      - Added "sat -show-regs -show-public -show-all"
 417      - Added "write_json" (Native Yosys JSON format)
 418      - Added "write_blif -attr"
 419      - Added "dffinit"
 420      - Added "chparam"
 421      - Added "muxcover"
 422      - Added "pmuxtree"
 423      - Added memory_bram "make_outreg" feature
 424      - Added "splice -wires"
 425      - Added "dff2dffe -direct-match"
 426      - Added simplemap $lut support
 427      - Added "read_blif"
 428      - Added "opt_share -share_all"
 429      - Added "aigmap"
 430      - Added "write_smt2 -mem -regs -wires"
 431      - Added "memory -nordff"
 432      - Added "write_smv"
 433      - Added "synth -nordff -noalumacc"
 434      - Added "rename -top new_name"
 435      - Added "opt_const -clkinv"
 436      - Added "synth -nofsm"
 437      - Added "miter -assert"
 438      - Added "read_verilog -noautowire"
 439      - Added "read_verilog -nodpi"
 440      - Added "tribuf"
 441      - Added "lut2mux"
 442      - Added "nlutmap"
 443      - Added "qwp"
 444      - Added "test_cell -noeval"
 445      - Added "edgetypes"
 446      - Added "equiv_struct"
 447      - Added "equiv_purge"
 448      - Added "equiv_mark"
 449      - Added "equiv_add -try -cell"
 450      - Added "singleton"
 451      - Added "abc -g -luts"
 452      - Added "torder"
 453      - Added "write_blif -cname"
 454      - Added "submod -copy"
 455      - Added "dffsr2dff"
 456      - Added "stat -liberty"
 457
 458  * Synthesis metacommands
 459      - Various improvements in synth_xilinx
 460      - Added synth_ice40 and synth_greenpak4
 461      - Added "prep" metacommand for "synthesis lite"
 462
 463  * Cell library changes
 464      - Added cell types to "help" system
 465      - Added $meminit cell type
 466      - Added $assume cell type
 467      - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
 468      - Added $tribuf and $_TBUF_ cell types
 469      - Added read-enable to memory model
 470
 471  * YosysJS
 472      - Various improvements in emscripten build
 473      - Added alternative webworker-based JS API
 474      - Added a few example applications
 475
 476
 477 Yosys 0.4 .. Yosys 0.5
 478 ----------------------
 479
 480  * API changes
 481      - Added log_warning()
 482      - Added eval_select_args() and eval_select_op()
 483      - Added cell->known(), cell->input(portname), cell->output(portname)
 484      - Skip blackbox modules in design->selected_modules()
 485      - Replaced std::map<> and std::set<> with dict<> and pool<>
 486      - New SigSpec::extend() is what used to be SigSpec::extend_u0()
 487      - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
 488
 489  * Cell library changes
 490      - Added flip-flops with enable ($dffe etc.)
 491      - Added $equiv cells for equivalence checking framework
 492
 493  * Various
 494      - Updated ABC to hg rev 61ad5f908c03
 495      - Added clock domain partitioning to ABC pass
 496      - Improved plugin building (see "yosys-config --build")
 497      - Added ENABLE_NDEBUG Makefile flag for high-performance builds
 498      - Added "yosys -d", "yosys -L" and other driver improvements
 499      - Added support for multi-bit (array) cell ports to "write_edif"
 500      - Now printing most output to stdout, not stderr
 501      - Added "onehot" attribute (set by "fsm_map")
 502      - Various performance improvements
 503      - Vastly improved Xilinx flow
 504      - Added "make unsintall"
 505
 506  * Equivalence checking
 507      - Added equivalence checking commands:
 508          equiv_make equiv_simple equiv_status
 509          equiv_induct equiv_miter
 510          equiv_add equiv_remove
 511
 512  * Block RAM support:
 513      - Added "memory_bram" command
 514      - Added BRAM support to Xilinx flow
 515
 516  * Other New Commands and Options
 517      - Added "dff2dffe"
 518      - Added "fsm -encfile"
 519      - Added "dfflibmap -prepare"
 520      - Added "write_blid -unbuf -undef -blackbox"
 521      - Added "write_smt2" for writing SMT-LIBv2 files
 522      - Added "test_cell -w -muxdiv"
 523      - Added "select -read"
 524
 525
 526 Yosys 0.3.0 .. Yosys 0.4
 527 ------------------------
 528
 529  * Platform Support
 530      - Added support for mxe-based cross-builds for win32
 531      - Added sourcecode-export as VisualStudio project
 532      - Added experimental EMCC (JavaScript) support
 533
 534  * Verilog Frontend
 535      - Added -sv option for SystemVerilog (and automatic *.sv file support)
 536      - Added support for real-valued constants and constant expressions
 537      - Added support for non-standard "via_celltype" attribute on task/func
 538      - Added support for non-standard "module mod_name(...);" syntax
 539      - Added support for non-standard """ macro bodies
 540      - Added support for array with more than one dimension
 541      - Added support for $readmemh and $readmemb
 542      - Added support for DPI functions
 543
 544  * Changes in internal cell library
 545      - Added $shift and $shiftx cell types
 546      - Added $alu, $lcu, $fa and $macc cell types
 547      - Removed $bu0 and $safe_pmux cell types
 548      - $mem/$memwr WR_EN input is now a per-data-bit enable signal
 549      - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
 550      - Renamed ports of $lut cells (from I->O to A->Y)
 551      - Renamed $_INV_ to $_NOT_
 552
 553  * Changes for simple synthesis flows
 554      - There is now a "synth" command with a recommended default script
 555      - Many improvements in synthesis of arithmetic functions to gates
 556          - Multipliers and adders with many operands are using carry-save adder trees
 557          - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
 558      - Various new high-level optimizations on RTL netlist
 559      - Various improvements in FSM optimization
 560      - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
 561
 562  * Changes in internal APIs and RTLIL
 563      - Added log_id() and log_cell() helper functions
 564      - Added function-like cell creation helpers
 565      - Added GetSize() function (like .size() but with int)
 566      - Major refactoring of RTLIL::Module and related classes
 567      - Major refactoring of RTLIL::SigSpec and related classes
 568      - Now RTLIL::IdString is essentially an int
 569      - Added macros for code coverage counters
 570      - Added some Makefile magic for pretty make logs
 571      - Added "kernel/yosys.h" with all the core definitions
 572      - Changed a lot of code from FILE* to c++ streams
 573      - Added RTLIL::Monitor API and "trace" command
 574      - Added "Yosys" C++ namespace
 575
 576  * Changes relevant to SAT solving
 577      - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
 578      - Added native ezSAT support for vector shift ops
 579      - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
 580
 581  * New commands (or large improvements to commands)
 582      - Added "synth" command with default script
 583      - Added "share" (finally some real resource sharing)
 584      - Added "memory_share" (reduce number of ports on memories)
 585      - Added "wreduce" and "alumacc" commands
 586      - Added "opt -keepdc -fine -full -fast"
 587      - Added some "test_*" commands
 588
 589  * Various other changes
 590      - Added %D and %c select operators
 591      - Added support for labels in yosys scripts
 592      - Added support for here-documents in yosys scripts
 593      - Support "+/" prefix for files from proc_share_dir
 594      - Added "autoidx" statement to ilang language
 595      - Switched from "yosys-svgviewer" to "xdot"
 596      - Renamed "stdcells.v" to "techmap.v"
 597      - Various bug fixes and small improvements
 598      - Improved welcome and bye messages
 599
 600
 601 Yosys 0.2.0 .. Yosys 0.3.0
 602 --------------------------
 603
 604  * Driver program and overall behavior:
 605      - Added "design -push" and "design -pop"
 606      - Added "tee" command for redirecting log output
 607
 608  * Changes in the internal cell library:
 609      - Added $dlatchsr and $_DLATCHSR_???_ cell types
 610
 611  * Improvements in Verilog frontend:
 612      - Improved support for const functions (case, always, repeat)
 613      - The generate..endgenerate keywords are now optional
 614      - Added support for arrays of module instances
 615      - Added support for "`default_nettype" directive
 616      - Added support for "`line" directive
 617
 618  * Other front- and back-ends:
 619      - Various changes to "write_blif" options
 620      - Various improvements in EDIF backend
 621      - Added "vhdl2verilog" pseudo-front-end
 622      - Added "verific" pseudo-front-end
 623
 624  * Improvements in technology mapping:
 625      - Added support for recursive techmap
 626      - Added CONSTMSK and CONSTVAL features to techmap
 627      - Added _TECHMAP_CONNMAP_*_ feature to techmap
 628      - Added _TECHMAP_REPLACE_ feature to techmap
 629      - Added "connwrappers" command for wrap-extract-unwrap method
 630      - Added "extract -map %<design_name>" feature
 631      - Added "extract -ignore_param ..." and "extract -ignore_parameters"
 632      - Added "techmap -max_iter" option
 633
 634  * Improvements to "eval" and "sat" framework:
 635      - Now include a copy of Minisat (with build fixes applied)
 636      - Switched to Minisat::SimpSolver as SAT back-end
 637      - Added "sat -dump_vcd" feature
 638      - Added "sat -dump_cnf" feature
 639      - Added "sat -initsteps <N>" feature
 640      - Added "freduce -stop <N>" feature
 641      - Added "freduce -dump <prefix>" feature
 642
 643  * Integration with ABC:
 644      - Updated ABC rev to 7600ffb9340c
 645
 646  * Improvements in the internal APIs:
 647      - Added RTLIL::Module::add... helper methods
 648      - Various build fixes for OSX (Darwin) and OpenBSD
 649
 650
 651 Yosys 0.1.0 .. Yosys 0.2.0
 652 --------------------------
 653
 654  * Changes to the driver program:
 655      - Added "yosys -h" and "yosys -H"
 656      - Added support for backslash line continuation in scripts
 657      - Added support for #-comments in same line as command
 658      - Added "echo" and "log" commands
 659
 660  * Improvements in Verilog frontend:
 661      - Added support for local registers in named blocks
 662      - Added support for "case" in "generate" blocks
 663      - Added support for $clog2 system function
 664      - Added support for basic SystemVerilog assert statements
 665      - Added preprocessor support for macro arguments
 666      - Added preprocessor support for `elsif statement
 667      - Added "verilog_defaults" command
 668      - Added read_verilog -icells option
 669      - Added support for constant sizes from parameters
 670      - Added "read_verilog -setattr"
 671      - Added support for function returning 'integer'
 672      - Added limited support for function calls in parameter values
 673      - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
 674
 675  * Other front- and back-ends:
 676      - Added BTOR backend
 677      - Added Liberty frontend
 678
 679  * Improvements in technology mapping:
 680      - The "dfflibmap" command now strongly prefers solutions with
 681            no inverters in clock paths
 682      - The "dfflibmap" command now prefers cells with smaller area
 683      - Added support for multiple -map options to techmap
 684      - Added "dfflibmap" support for //-comments in liberty files
 685      - Added "memory_unpack" command to revert "memory_collect"
 686      - Added standard techmap rule "techmap -share_map pmux2mux.v"
 687      - Added "iopadmap -bits"
 688      - Added "setundef" command
 689      - Added "hilomap" command
 690
 691  * Changes in the internal cell library:
 692      - Major rewrite of simlib.v for better compatibility with other tools
 693      - Added PRIORITY parameter to $memwr cells
 694      - Added TRANSPARENT parameter to $memrd cells
 695      - Added RD_TRANSPARENT parameter to $mem cells
 696      - Added $bu0 cell (always 0-extend, even undef MSB)
 697      - Added $assert cell type
 698      - Added $slice and $concat cell types
 699
 700  * Integration with ABC:
 701      - Updated ABC to hg rev 2058c8ccea68
 702      - Tighter integration of ABC build with Yosys build. The make
 703            targets 'make abc' and 'make install-abc' are now obsolete.
 704      - Added support for passing FFs from one clock domain through ABC
 705      - Now always use BLIF as exchange format with ABC
 706      - Added support for "abc -script +<command_sequence>"
 707      - Improved standard ABC recipe
 708      - Added support for "keep" attribute to abc command
 709      - Added "abc -dff / -clk / -keepff" options
 710
 711  * Improvements to "eval" and "sat" framework:
 712      - Added support for "0" and "~0" in right-hand side -set expressions
 713      - Added "eval -set-undef" and "eval -table"
 714      - Added "sat -set-init" and "sat -set-init-*" for sequential problems
 715      - Added undef support to SAT solver, incl. various new "sat" options
 716      - Added correct support for === and !== for "eval" and "sat"
 717      - Added "sat -tempinduct" (default -seq is now non-induction sequential)
 718      - Added "sat -prove-asserts"
 719      - Complete rewrite of the 'freduce' command
 720      - Added "miter" command
 721      - Added "sat -show-inputs" and "sat -show-outputs"
 722      - Added "sat -ignore_unknown_cells" (now produce an error by default)
 723      - Added "sat -falsify"
 724      - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
 725      - Added "expose" command
 726      - Added support for @<sel_name> to sat and eval signal expressions
 727
 728  * Changes in the 'make test' framework and auxiliary test tools:
 729      - Added autotest.sh -p and -f options
 730      - Replaced autotest.sh ISIM support with XSIM support
 731      - Added test cases for SAT framework
 732
 733  * Added "abbreviated IDs":
 734      - Now $<something>$foo can be abbreviated as $foo.
 735      - Usually this last part is a unique id (from RTLIL::autoidx)
 736      - This abbreviated IDs are now also used in "show" output
 737
 738  * Other changes to selection framework:
 739      - Now */ is optional in */<mode>:<arg> expressions
 740      - Added "select -assert-none" and "select -assert-any"
 741      - Added support for matching modules by attribute (A:<expr>)
 742      - Added "select -none"
 743      - Added support for r:<expr> pattern for matching cell parameters
 744      - Added support for !=, <, <=, >=, > for attribute and parameter matching
 745      - Added support for %s for selecting sub-modules
 746      - Added support for %m for expanding selections to whole modules
 747      - Added support for i:*, o:* and x:* pattern for selecting module ports
 748      - Added support for s:<expr> pattern for matching wire width
 749      - Added support for %a operation to select wire aliases
 750
 751  * Various other changes to commands and options:
 752      - The "ls" command now supports wildcards
 753      - Added "show -pause" and "show -format dot"
 754      - Added "show -color" support for cells
 755      - Added "show -label" and "show -notitle"
 756      - Added "dump -m" and "dump -n"
 757      - Added "history" command
 758      - Added "rename -hide"
 759      - Added "connect" command
 760      - Added "splitnets -driver"
 761      - Added "opt_const -mux_undef"
 762      - Added "opt_const -mux_bool"
 763      - Added "opt_const -undriven"
 764      - Added "opt -mux_undef -mux_bool -undriven -purge"
 765      - Added "hierarchy -libdir"
 766      - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
 767      - Added "delete" command
 768      - Added "dump -append"
 769      - Added "setattr" and "setparam" commands
 770      - Added "design -stash/-copy-from/-copy-to"
 771      - Added "copy" command
 772      - Added "splice" command
 773