2 List of major changes and improvements between releases
3 =======================================================
6 Yosys 0.8 .. Yosys 0.8-dev
7 --------------------------
10 - Added $changed support to read_verilog
11 - Added "write_edif -attrprop"
12 - Added "ice40_unlut" pass
13 - Added "opt_lut" pass
14 - Added "synth_ice40 -relut"
15 - Added "synth_ice40 -noabc"
16 - Added "gate2lut.v" techmap rule
18 - Added "equiv_opt" pass
19 - Added "read_aiger" frontend
20 - Added "muxcover -mux{4,8,16}=<cost>"
21 - Added "muxcover -dmux=<cost>"
22 - Added "muxcover -nopartial"
23 - Added "muxpack" pass
24 - Added "pmux2shiftx -norange"
25 - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
26 - Fixed sign extension of unsized constants with 'bx and 'bz MSB
29 Yosys 0.7 .. Yosys 0.8
30 ----------------------
33 - Many bugfixes and small improvements
34 - Strip debug symbols from installed binary
35 - Replace -ignore_redef with -[no]overwrite in front-ends
36 - Added write_verilog hex dump support, add -nohex option
37 - Added "write_verilog -decimal"
38 - Added "scc -set_attr"
39 - Added "verilog_defines" command
40 - Remember defines from one read_verilog to next
41 - Added support for hierarchical defparam
42 - Added FIRRTL back-end
43 - Improved ABC default scripts
44 - Added "design -reset-vlog"
45 - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
46 - Added Verilog $rtoi and $itor support
47 - Added "check -initdrv"
48 - Added "read_blif -wideports"
49 - Added support for systemVerilog "++" and "--" operators
50 - Added support for SystemVerilog unique, unique0, and priority case
51 - Added "write_edif" options for edif "flavors"
52 - Added support for resetall compiler directive
53 - Added simple C beck-end (bitwise combinatorical only atm)
54 - Added $_ANDNOT_ and $_ORNOT_ cell types
55 - Added cell library aliases to "abc -g"
56 - Added "setundef -anyseq"
57 - Added "chtype" command
58 - Added "design -import"
59 - Added "write_table" command
60 - Added "read_json" command
62 - Added "extract_fa" and "extract_reduce" commands
63 - Added "extract_counter" command
64 - Added "opt_demorgan" command
65 - Added support for $size and $bits SystemVerilog functions
66 - Added "blackbox" command
68 - Added support for editline as replacement for readline
69 - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
70 - Added "yosys -E" for creating Makefile dependencies files
71 - Added "synth -noshare"
72 - Added "memory_nordff"
73 - Added "setundef -undef -expose -anyconst"
74 - Added "expose -input"
75 - Added specify/specparam parser support (simply ignore them)
76 - Added "write_blif -inames -iattr"
77 - Added "hierarchy -simcheck"
78 - Added an option to statically link abc into yosys
79 - Added protobuf back-end
80 - Added BLIF parsing support for .conn and .cname
81 - Added read_verilog error checking for reg/wire/logic misuse
82 - Added "make coverage" and ENABLE_GCOV build option
84 * Changes in Yosys APIs
85 - Added ConstEval defaultval feature
86 - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
87 - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
88 - Added log_file_warning() and log_file_error() functions
92 - Added "yosys-smtbmc --aig"
93 - Added "always <positive_int>" to .smtc format
94 - Added $cover cell type and support for cover properties
95 - Added $fair/$live cell type and support for liveness properties
96 - Added smtbmc support for memory vcd dumping
97 - Added "chformal" command
98 - Added "write_smt2 -stbv" and "write_smt2 -stdt"
99 - Fix equiv_simple, old behavior now available with "equiv_simple -short"
100 - Change to Yices2 as default SMT solver (it is GPL now)
101 - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
102 - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
103 - Added a brand new "write_btor" command for BTOR2
104 - Added clk2fflogic memory support and other improvements
105 - Added "async memory write" support to write_smt2
106 - Simulate clock toggling in yosys-smtbmc VCD output
107 - Added $allseq/$allconst cells for EA-solving
108 - Make -nordff the default in "prep"
109 - Added (* gclk *) attribute
110 - Added "async2sync" pass for single-clock designs with async resets
113 - Many improvements in Verific front-end
114 - Added proper handling of concurent SVA properties
115 - Map "const" and "rand const" to $anyseq/$anyconst
116 - Added "verific -import -flatten" and "verific -import -extnets"
117 - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
118 - Remove PSL support (because PSL has been removed in upstream Verific)
119 - Improve integration with "hierarchy" command design elaboration
120 - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
121 - Added simpilied "read" command that automatically uses verific if available
122 - Added "verific -set-<severity> <msg_id>.."
123 - Added "verific -work <libname>"
126 - Added initial Coolrunner-II support
127 - Added initial eASIC support
128 - Added initial ECP5 support
131 - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
134 - Add "synth_ice40 -vpr"
135 - Add "synth_ice40 -nodffe"
136 - Add "synth_ice40 -json"
137 - Add Support for UltraPlus cells
139 * MAX10 and Cyclone IV Support
140 - Added initial version of metacommand "synth_intel".
141 - Improved write_verilog command to produce VQM netlist for Quartus Prime.
142 - Added support for MAX10 FPGA family synthesis.
143 - Added support for Cyclone IV family synthesis.
144 - Added example of implementation for DE2i-150 board.
145 - Added example of implementation for MAX10 development kit.
146 - Added LFSR example from Asic World.
147 - Added "dffinit -highlow" for mapping to Intel primitives
150 Yosys 0.6 .. Yosys 0.7
151 ----------------------
154 - Added "yosys -D" feature
155 - Added support for installed plugins in $(DATDIR)/plugins/
156 - Renamed opt_const to opt_expr
157 - Renamed opt_share to opt_merge
158 - Added "prep -flatten" and "synth -flatten"
159 - Added "prep -auto-top" and "synth -auto-top"
160 - Using "mfs" and "lutpack" in ABC lut mapping
161 - Support for abstract modules in chparam
162 - Cleanup abstract modules at end of "hierarchy -top"
163 - Added tristate buffer support to iopadmap
164 - Added opt_expr support for div/mod by power-of-two
165 - Added "select -assert-min <N> -assert-max <N>"
166 - Added "attrmvcp" pass
167 - Added "attrmap" command
168 - Added "tee +INT -INT"
170 - Added "setparam -type"
171 - Added "shregmap" pass
172 - Added "setundef -init"
173 - Added "nlutmap -assert"
174 - Added $sop cell type and "abc -sop -I <num> -P <num>"
175 - Added "dc2" to default ABC scripts
177 - Added "insbuf" command
178 - Added "prep -nomem"
179 - Added "opt_rmdff -keepdc"
180 - Added "prep -nokeepdc"
181 - Added initial version of "synth_gowin"
182 - Added "fsm_expand -full"
183 - Added support for fsm_encoding="user"
184 - Many improvements in GreenPAK4 support
185 - Added black box modules for all Xilinx 7-series lib cells
186 - Added synth_ice40 support for latches via logic loops
187 - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
190 - Added ABCEXTERNAL and ABCURL make variables
191 - Added BINDIR, LIBDIR, and DATDIR make variables
192 - Added PKG_CONFIG make variable
193 - Added SEED make variable (for "make test")
194 - Added YOSYS_VER_STR make variable
195 - Updated min GCC requirement to GCC 4.8
196 - Updated required Bison version to Bison 3.x
199 - Added ast.h to exported headers
200 - Added ScriptPass helper class for script-like passes
201 - Added CellEdgesDatabase API
203 * Front-ends and Back-ends
204 - Added filename glob support to all front-ends
205 - Added avail (black-box) module params to ilang format
206 - Added $display %m support
207 - Added support for $stop Verilog system task
208 - Added support for SystemVerilog packages
209 - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
210 - Added support for "active high" and "active low" latches in read_blif and write_blif
211 - Use init value "2" for all uninitialized FFs in BLIF back-end
212 - Added "read_blif -sop"
213 - Added "write_blif -noalias"
214 - Added various write_blif options for VTR support
215 - write_json: also write module attributes.
216 - Added "write_verilog -nodec -nostr -defparam"
217 - Added "read_verilog -norestrict -assume-asserts"
218 - Added support for bus interfaces to "read_liberty -lib"
219 - Added liberty parser support for types within cell decls
220 - Added "write_verilog -renameprefix -v"
221 - Added "write_edif -nogndvcc"
223 * Formal Verification
224 - Support for hierarchical designs in smt2 back-end
225 - Yosys-smtbmc: Support for hierarchical VCD dumping
226 - Added $initstate cell type and vlog function
227 - Added $anyconst and $anyseq cell types and vlog functions
228 - Added printing of code loc of failed asserts to yosys-smtbmc
229 - Added memory_memx pass, "memory -memx", and "prep -memx"
230 - Added "proc_mux -ifx"
231 - Added "yosys-smtbmc -g"
232 - Deprecated "write_smt2 -regs" (by default on now)
233 - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
234 - Added support for memories to smtio.py
235 - Added "yosys-smtbmc --dump-vlogtb"
236 - Added "yosys-smtbmc --smtc --dump-smtc"
237 - Added "yosys-smtbmc --dump-all"
238 - Added assertpmux command
239 - Added "yosys-smtbmc --unroll"
240 - Added $past, $stable, $rose, $fell SVA functions
241 - Added "yosys-smtbmc --noinfo and --dummy"
242 - Added "yosys-smtbmc --noincr"
243 - Added "yosys-smtbmc --cex <filename>"
244 - Added $ff and $_FF_ cell types
245 - Added $global_clock verilog syntax support for creating $ff cells
249 Yosys 0.5 .. Yosys 0.6
250 ----------------------
253 - Added Contributor Covenant Code of Conduct
254 - Various improvements in dict<> and pool<>
255 - Added hashlib::mfp and refactored SigMap
256 - Improved support for reals as module parameters
257 - Various improvements in SMT2 back-end
258 - Added "keep_hierarchy" attribute
259 - Verilog front-end: define `BLACKBOX in -lib mode
260 - Added API for converting internal cells to AIGs
261 - Added ENABLE_LIBYOSYS Makefile option
262 - Removed "techmap -share_map" (use "-map +/filename" instead)
263 - Switched all Python scripts to Python 3
264 - Added support for $display()/$write() and $finish() to Verilog front-end
265 - Added "yosys-smtbmc" formal verification flow
266 - Added options for clang sanitizers to Makefile
268 * New commands and options
269 - Added "scc -expect <N> -nofeedback"
270 - Added "proc_dlatch"
272 - Added "select %xe %cie %coe %M %C %R"
273 - Added "sat -dump_json" (WaveJSON format)
274 - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
275 - Added "sat -stepsize" and "sat -tempinduct-step"
276 - Added "sat -show-regs -show-public -show-all"
277 - Added "write_json" (Native Yosys JSON format)
278 - Added "write_blif -attr"
283 - Added memory_bram "make_outreg" feature
284 - Added "splice -wires"
285 - Added "dff2dffe -direct-match"
286 - Added simplemap $lut support
288 - Added "opt_share -share_all"
290 - Added "write_smt2 -mem -regs -wires"
291 - Added "memory -nordff"
293 - Added "synth -nordff -noalumacc"
294 - Added "rename -top new_name"
295 - Added "opt_const -clkinv"
296 - Added "synth -nofsm"
297 - Added "miter -assert"
298 - Added "read_verilog -noautowire"
299 - Added "read_verilog -nodpi"
304 - Added "test_cell -noeval"
306 - Added "equiv_struct"
307 - Added "equiv_purge"
309 - Added "equiv_add -try -cell"
311 - Added "abc -g -luts"
313 - Added "write_blif -cname"
314 - Added "submod -copy"
316 - Added "stat -liberty"
318 * Synthesis metacommands
319 - Various improvements in synth_xilinx
320 - Added synth_ice40 and synth_greenpak4
321 - Added "prep" metacommand for "synthesis lite"
323 * Cell library changes
324 - Added cell types to "help" system
325 - Added $meminit cell type
326 - Added $assume cell type
327 - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
328 - Added $tribuf and $_TBUF_ cell types
329 - Added read-enable to memory model
332 - Various improvements in emscripten build
333 - Added alternative webworker-based JS API
334 - Added a few example applications
337 Yosys 0.4 .. Yosys 0.5
338 ----------------------
341 - Added log_warning()
342 - Added eval_select_args() and eval_select_op()
343 - Added cell->known(), cell->input(portname), cell->output(portname)
344 - Skip blackbox modules in design->selected_modules()
345 - Replaced std::map<> and std::set<> with dict<> and pool<>
346 - New SigSpec::extend() is what used to be SigSpec::extend_u0()
347 - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
349 * Cell library changes
350 - Added flip-flops with enable ($dffe etc.)
351 - Added $equiv cells for equivalence checking framework
354 - Updated ABC to hg rev 61ad5f908c03
355 - Added clock domain partitioning to ABC pass
356 - Improved plugin building (see "yosys-config --build")
357 - Added ENABLE_NDEBUG Makefile flag for high-performance builds
358 - Added "yosys -d", "yosys -L" and other driver improvements
359 - Added support for multi-bit (array) cell ports to "write_edif"
360 - Now printing most output to stdout, not stderr
361 - Added "onehot" attribute (set by "fsm_map")
362 - Various performance improvements
363 - Vastly improved Xilinx flow
364 - Added "make unsintall"
366 * Equivalence checking
367 - Added equivalence checking commands:
368 equiv_make equiv_simple equiv_status
369 equiv_induct equiv_miter
370 equiv_add equiv_remove
373 - Added "memory_bram" command
374 - Added BRAM support to Xilinx flow
376 * Other New Commands and Options
378 - Added "fsm -encfile"
379 - Added "dfflibmap -prepare"
380 - Added "write_blid -unbuf -undef -blackbox"
381 - Added "write_smt2" for writing SMT-LIBv2 files
382 - Added "test_cell -w -muxdiv"
383 - Added "select -read"
386 Yosys 0.3.0 .. Yosys 0.4
387 ------------------------
390 - Added support for mxe-based cross-builds for win32
391 - Added sourcecode-export as VisualStudio project
392 - Added experimental EMCC (JavaScript) support
395 - Added -sv option for SystemVerilog (and automatic *.sv file support)
396 - Added support for real-valued constants and constant expressions
397 - Added support for non-standard "via_celltype" attribute on task/func
398 - Added support for non-standard "module mod_name(...);" syntax
399 - Added support for non-standard """ macro bodies
400 - Added support for array with more than one dimension
401 - Added support for $readmemh and $readmemb
402 - Added support for DPI functions
404 * Changes in internal cell library
405 - Added $shift and $shiftx cell types
406 - Added $alu, $lcu, $fa and $macc cell types
407 - Removed $bu0 and $safe_pmux cell types
408 - $mem/$memwr WR_EN input is now a per-data-bit enable signal
409 - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
410 - Renamed ports of $lut cells (from I->O to A->Y)
411 - Renamed $_INV_ to $_NOT_
413 * Changes for simple synthesis flows
414 - There is now a "synth" command with a recommended default script
415 - Many improvements in synthesis of arithmetic functions to gates
416 - Multipliers and adders with many operands are using carry-save adder trees
417 - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
418 - Various new high-level optimizations on RTL netlist
419 - Various improvements in FSM optimization
420 - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
422 * Changes in internal APIs and RTLIL
423 - Added log_id() and log_cell() helper functions
424 - Added function-like cell creation helpers
425 - Added GetSize() function (like .size() but with int)
426 - Major refactoring of RTLIL::Module and related classes
427 - Major refactoring of RTLIL::SigSpec and related classes
428 - Now RTLIL::IdString is essentially an int
429 - Added macros for code coverage counters
430 - Added some Makefile magic for pretty make logs
431 - Added "kernel/yosys.h" with all the core definitions
432 - Changed a lot of code from FILE* to c++ streams
433 - Added RTLIL::Monitor API and "trace" command
434 - Added "Yosys" C++ namespace
436 * Changes relevant to SAT solving
437 - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
438 - Added native ezSAT support for vector shift ops
439 - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
441 * New commands (or large improvements to commands)
442 - Added "synth" command with default script
443 - Added "share" (finally some real resource sharing)
444 - Added "memory_share" (reduce number of ports on memories)
445 - Added "wreduce" and "alumacc" commands
446 - Added "opt -keepdc -fine -full -fast"
447 - Added some "test_*" commands
449 * Various other changes
450 - Added %D and %c select operators
451 - Added support for labels in yosys scripts
452 - Added support for here-documents in yosys scripts
453 - Support "+/" prefix for files from proc_share_dir
454 - Added "autoidx" statement to ilang language
455 - Switched from "yosys-svgviewer" to "xdot"
456 - Renamed "stdcells.v" to "techmap.v"
457 - Various bug fixes and small improvements
458 - Improved welcome and bye messages
461 Yosys 0.2.0 .. Yosys 0.3.0
462 --------------------------
464 * Driver program and overall behavior:
465 - Added "design -push" and "design -pop"
466 - Added "tee" command for redirecting log output
468 * Changes in the internal cell library:
469 - Added $dlatchsr and $_DLATCHSR_???_ cell types
471 * Improvements in Verilog frontend:
472 - Improved support for const functions (case, always, repeat)
473 - The generate..endgenerate keywords are now optional
474 - Added support for arrays of module instances
475 - Added support for "`default_nettype" directive
476 - Added support for "`line" directive
478 * Other front- and back-ends:
479 - Various changes to "write_blif" options
480 - Various improvements in EDIF backend
481 - Added "vhdl2verilog" pseudo-front-end
482 - Added "verific" pseudo-front-end
484 * Improvements in technology mapping:
485 - Added support for recursive techmap
486 - Added CONSTMSK and CONSTVAL features to techmap
487 - Added _TECHMAP_CONNMAP_*_ feature to techmap
488 - Added _TECHMAP_REPLACE_ feature to techmap
489 - Added "connwrappers" command for wrap-extract-unwrap method
490 - Added "extract -map %<design_name>" feature
491 - Added "extract -ignore_param ..." and "extract -ignore_parameters"
492 - Added "techmap -max_iter" option
494 * Improvements to "eval" and "sat" framework:
495 - Now include a copy of Minisat (with build fixes applied)
496 - Switched to Minisat::SimpSolver as SAT back-end
497 - Added "sat -dump_vcd" feature
498 - Added "sat -dump_cnf" feature
499 - Added "sat -initsteps <N>" feature
500 - Added "freduce -stop <N>" feature
501 - Added "freduce -dump <prefix>" feature
503 * Integration with ABC:
504 - Updated ABC rev to 7600ffb9340c
506 * Improvements in the internal APIs:
507 - Added RTLIL::Module::add... helper methods
508 - Various build fixes for OSX (Darwin) and OpenBSD
511 Yosys 0.1.0 .. Yosys 0.2.0
512 --------------------------
514 * Changes to the driver program:
515 - Added "yosys -h" and "yosys -H"
516 - Added support for backslash line continuation in scripts
517 - Added support for #-comments in same line as command
518 - Added "echo" and "log" commands
520 * Improvements in Verilog frontend:
521 - Added support for local registers in named blocks
522 - Added support for "case" in "generate" blocks
523 - Added support for $clog2 system function
524 - Added support for basic SystemVerilog assert statements
525 - Added preprocessor support for macro arguments
526 - Added preprocessor support for `elsif statement
527 - Added "verilog_defaults" command
528 - Added read_verilog -icells option
529 - Added support for constant sizes from parameters
530 - Added "read_verilog -setattr"
531 - Added support for function returning 'integer'
532 - Added limited support for function calls in parameter values
533 - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
535 * Other front- and back-ends:
537 - Added Liberty frontend
539 * Improvements in technology mapping:
540 - The "dfflibmap" command now strongly prefers solutions with
541 no inverters in clock paths
542 - The "dfflibmap" command now prefers cells with smaller area
543 - Added support for multiple -map options to techmap
544 - Added "dfflibmap" support for //-comments in liberty files
545 - Added "memory_unpack" command to revert "memory_collect"
546 - Added standard techmap rule "techmap -share_map pmux2mux.v"
547 - Added "iopadmap -bits"
548 - Added "setundef" command
549 - Added "hilomap" command
551 * Changes in the internal cell library:
552 - Major rewrite of simlib.v for better compatibility with other tools
553 - Added PRIORITY parameter to $memwr cells
554 - Added TRANSPARENT parameter to $memrd cells
555 - Added RD_TRANSPARENT parameter to $mem cells
556 - Added $bu0 cell (always 0-extend, even undef MSB)
557 - Added $assert cell type
558 - Added $slice and $concat cell types
560 * Integration with ABC:
561 - Updated ABC to hg rev 2058c8ccea68
562 - Tighter integration of ABC build with Yosys build. The make
563 targets 'make abc' and 'make install-abc' are now obsolete.
564 - Added support for passing FFs from one clock domain through ABC
565 - Now always use BLIF as exchange format with ABC
566 - Added support for "abc -script +<command_sequence>"
567 - Improved standard ABC recipe
568 - Added support for "keep" attribute to abc command
569 - Added "abc -dff / -clk / -keepff" options
571 * Improvements to "eval" and "sat" framework:
572 - Added support for "0" and "~0" in right-hand side -set expressions
573 - Added "eval -set-undef" and "eval -table"
574 - Added "sat -set-init" and "sat -set-init-*" for sequential problems
575 - Added undef support to SAT solver, incl. various new "sat" options
576 - Added correct support for === and !== for "eval" and "sat"
577 - Added "sat -tempinduct" (default -seq is now non-induction sequential)
578 - Added "sat -prove-asserts"
579 - Complete rewrite of the 'freduce' command
580 - Added "miter" command
581 - Added "sat -show-inputs" and "sat -show-outputs"
582 - Added "sat -ignore_unknown_cells" (now produce an error by default)
583 - Added "sat -falsify"
584 - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
585 - Added "expose" command
586 - Added support for @<sel_name> to sat and eval signal expressions
588 * Changes in the 'make test' framework and auxiliary test tools:
589 - Added autotest.sh -p and -f options
590 - Replaced autotest.sh ISIM support with XSIM support
591 - Added test cases for SAT framework
593 * Added "abbreviated IDs":
594 - Now $<something>$foo can be abbreviated as $foo.
595 - Usually this last part is a unique id (from RTLIL::autoidx)
596 - This abbreviated IDs are now also used in "show" output
598 * Other changes to selection framework:
599 - Now */ is optional in */<mode>:<arg> expressions
600 - Added "select -assert-none" and "select -assert-any"
601 - Added support for matching modules by attribute (A:<expr>)
602 - Added "select -none"
603 - Added support for r:<expr> pattern for matching cell parameters
604 - Added support for !=, <, <=, >=, > for attribute and parameter matching
605 - Added support for %s for selecting sub-modules
606 - Added support for %m for expanding selections to whole modules
607 - Added support for i:*, o:* and x:* pattern for selecting module ports
608 - Added support for s:<expr> pattern for matching wire width
609 - Added support for %a operation to select wire aliases
611 * Various other changes to commands and options:
612 - The "ls" command now supports wildcards
613 - Added "show -pause" and "show -format dot"
614 - Added "show -color" support for cells
615 - Added "show -label" and "show -notitle"
616 - Added "dump -m" and "dump -n"
617 - Added "history" command
618 - Added "rename -hide"
619 - Added "connect" command
620 - Added "splitnets -driver"
621 - Added "opt_const -mux_undef"
622 - Added "opt_const -mux_bool"
623 - Added "opt_const -undriven"
624 - Added "opt -mux_undef -mux_bool -undriven -purge"
625 - Added "hierarchy -libdir"
626 - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
627 - Added "delete" command
628 - Added "dump -append"
629 - Added "setattr" and "setparam" commands
630 - Added "design -stash/-copy-from/-copy-to"
631 - Added "copy" command
632 - Added "splice" command