2 List of major changes and improvements between releases
3 =======================================================
10 - Added "yosys -D" feature
11 - Added support for installed plugins in $(DATDIR)/plugins/
12 - Renamed opt_const to opt_expr
13 - Renamed opt_share to opt_merge
14 - Added "prep -flatten" and "synth -flatten"
15 - Added "prep -auto-top" and "synth -auto-top"
16 - Using "mfs" and "lutpack" in ABC lut mapping
17 - Support for abstract modules in chparam
18 - Cleanup abstract modules at end of "hierarchy -top"
19 - Added tristate buffer support to iopadmap
20 - Added opt_expr support for div/mod by power-of-two
21 - Added "select -assert-min <N> -assert-max <N>"
22 - Added "attrmvcp" pass
23 - Added "attrmap" command
24 - Added "tee +INT -INT"
26 - Added "setparam -type"
27 - Added "shregmap" pass
28 - Added "setundef -init"
29 - Added "nlutmap -assert"
30 - Added $sop cell type and "abc -sop -I <num> -P <num>"
31 - Added "dc2" to default ABC scripts
33 - Added "insbuf" command
35 - Added "opt_rmdff -keepdc"
36 - Added "prep -nokeepdc"
37 - Added initial version of "synth_gowin"
38 - Added "fsm_expand -full"
39 - Added support for fsm_encoding="user"
40 - Many improvements in GreenPAK4 support
41 - Added black box modules for all Xilinx 7-series lib cells
42 - Added synth_ice40 support for latches via logic loops
43 - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
46 - Added ABCEXTERNAL and ABCURL make variables
47 - Added BINDIR, LIBDIR, and DATDIR make variables
48 - Added PKG_CONFIG make variable
49 - Added SEED make variable (for "make test")
50 - Added YOSYS_VER_STR make variable
51 - Updated min GCC requirement to GCC 4.8
52 - Updated required Bison version to Bison 3.x
55 - Added ast.h to exported headers
56 - Added ScriptPass helper class for script-like passes
57 - Added CellEdgesDatabase API
59 * Front-ends and Back-ends
60 - Added filename glob support to all front-ends
61 - Added avail (black-box) module params to ilang format
62 - Added $display %m support
63 - Added support for $stop Verilog system task
64 - Added support for SystemVerilog packages
65 - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
66 - Added support for "active high" and "active low" latches in read_blif and write_blif
67 - Use init value "2" for all uninitialized FFs in BLIF back-end
68 - Added "read_blif -sop"
69 - Added "write_blif -noalias"
70 - Added various write_blif options for VTR support
71 - write_json: also write module attributes.
72 - Added "write_verilog -nodec -nostr -defparam"
73 - Added "read_verilog -norestrict -assume-asserts"
74 - Added support for bus interfaces to "read_liberty -lib"
75 - Added liberty parser support for types within cell decls
76 - Added "write_verilog -renameprefix -v"
77 - Added "write_edif -nogndvcc"
80 - Support for hierarchical designs in smt2 back-end
81 - Yosys-smtbmc: Support for hierarchical VCD dumping
82 - Added $initstate cell type and vlog function
83 - Added $anyconst and $anyseq cell types and vlog functions
84 - Added printing of code loc of failed asserts to yosys-smtbmc
85 - Added memory_memx pass, "memory -memx", and "prep -memx"
86 - Added "proc_mux -ifx"
87 - Added "yosys-smtbmc -g"
88 - Deprecated "write_smt2 -regs" (by default on now)
89 - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
90 - Added support for memories to smtio.py
91 - Added "yosys-smtbmc --dump-vlogtb"
92 - Added "yosys-smtbmc --smtc --dump-smtc"
93 - Added "yosys-smtbmc --dump-all"
94 - Added assertpmux command
95 - Added "yosys-smtbmc --unroll"
96 - Added $past, $stable, $rose, $fell SVA functions
97 - Added "yosys-smtbmc --noinfo and --dummy"
98 - Added "yosys-smtbmc --noincr"
99 - Added "yosys-smtbmc --cex <filename>"
100 - Added $ff and $_FF_ cell types
101 - Added $global_clock verilog syntax support for creating $ff cells
105 Yosys 0.5 .. Yosys 0.6
106 ----------------------
109 - Added Contributor Covenant Code of Conduct
110 - Various improvements in dict<> and pool<>
111 - Added hashlib::mfp and refactored SigMap
112 - Improved support for reals as module parameters
113 - Various improvements in SMT2 back-end
114 - Added "keep_hierarchy" attribute
115 - Verilog front-end: define `BLACKBOX in -lib mode
116 - Added API for converting internal cells to AIGs
117 - Added ENABLE_LIBYOSYS Makefile option
118 - Removed "techmap -share_map" (use "-map +/filename" instead)
119 - Switched all Python scripts to Python 3
120 - Added support for $display()/$write() and $finish() to Verilog front-end
121 - Added "yosys-smtbmc" formal verification flow
122 - Added options for clang sanitizers to Makefile
124 * New commands and options
125 - Added "scc -expect <N> -nofeedback"
126 - Added "proc_dlatch"
128 - Added "select %xe %cie %coe %M %C %R"
129 - Added "sat -dump_json" (WaveJSON format)
130 - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
131 - Added "sat -stepsize" and "sat -tempinduct-step"
132 - Added "sat -show-regs -show-public -show-all"
133 - Added "write_json" (Native Yosys JSON format)
134 - Added "write_blif -attr"
139 - Added memory_bram "make_outreg" feature
140 - Added "splice -wires"
141 - Added "dff2dffe -direct-match"
142 - Added simplemap $lut support
144 - Added "opt_share -share_all"
146 - Added "write_smt2 -mem -regs -wires"
147 - Added "memory -nordff"
149 - Added "synth -nordff -noalumacc"
150 - Added "rename -top new_name"
151 - Added "opt_const -clkinv"
152 - Added "synth -nofsm"
153 - Added "miter -assert"
154 - Added "read_verilog -noautowire"
155 - Added "read_verilog -nodpi"
160 - Added "test_cell -noeval"
162 - Added "equiv_struct"
163 - Added "equiv_purge"
165 - Added "equiv_add -try -cell"
167 - Added "abc -g -luts"
169 - Added "write_blif -cname"
170 - Added "submod -copy"
172 - Added "stat -liberty"
174 * Synthesis metacommands
175 - Various improvements in synth_xilinx
176 - Added synth_ice40 and synth_greenpak4
177 - Added "prep" metacommand for "synthesis lite"
179 * Cell library changes
180 - Added cell types to "help" system
181 - Added $meminit cell type
182 - Added $assume cell type
183 - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
184 - Added $tribuf and $_TBUF_ cell types
185 - Added read-enable to memory model
188 - Various improvements in emscripten build
189 - Added alternative webworker-based JS API
190 - Added a few example applications
193 Yosys 0.4 .. Yosys 0.5
194 ----------------------
197 - Added log_warning()
198 - Added eval_select_args() and eval_select_op()
199 - Added cell->known(), cell->input(portname), cell->output(portname)
200 - Skip blackbox modules in design->selected_modules()
201 - Replaced std::map<> and std::set<> with dict<> and pool<>
202 - New SigSpec::extend() is what used to be SigSpec::extend_u0()
203 - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
205 * Cell library changes
206 - Added flip-flops with enable ($dffe etc.)
207 - Added $equiv cells for equivalence checking framework
210 - Updated ABC to hg rev 61ad5f908c03
211 - Added clock domain partitioning to ABC pass
212 - Improved plugin building (see "yosys-config --build")
213 - Added ENABLE_NDEBUG Makefile flag for high-performance builds
214 - Added "yosys -d", "yosys -L" and other driver improvements
215 - Added support for multi-bit (array) cell ports to "write_edif"
216 - Now printing most output to stdout, not stderr
217 - Added "onehot" attribute (set by "fsm_map")
218 - Various performance improvements
219 - Vastly improved Xilinx flow
220 - Added "make unsintall"
222 * Equivalence checking
223 - Added equivalence checking commands:
224 equiv_make equiv_simple equiv_status
225 equiv_induct equiv_miter
226 equiv_add equiv_remove
229 - Added "memory_bram" command
230 - Added BRAM support to Xilinx flow
232 * Other New Commands and Options
234 - Added "fsm -encfile"
235 - Added "dfflibmap -prepare"
236 - Added "write_blid -unbuf -undef -blackbox"
237 - Added "write_smt2" for writing SMT-LIBv2 files
238 - Added "test_cell -w -muxdiv"
239 - Added "select -read"
242 Yosys 0.3.0 .. Yosys 0.4
243 ------------------------
246 - Added support for mxe-based cross-builds for win32
247 - Added sourcecode-export as VisualStudio project
248 - Added experimental EMCC (JavaScript) support
251 - Added -sv option for SystemVerilog (and automatic *.sv file support)
252 - Added support for real-valued constants and constant expressions
253 - Added support for non-standard "via_celltype" attribute on task/func
254 - Added support for non-standard "module mod_name(...);" syntax
255 - Added support for non-standard """ macro bodies
256 - Added support for array with more than one dimension
257 - Added support for $readmemh and $readmemb
258 - Added support for DPI functions
260 * Changes in internal cell library
261 - Added $shift and $shiftx cell types
262 - Added $alu, $lcu, $fa and $macc cell types
263 - Removed $bu0 and $safe_pmux cell types
264 - $mem/$memwr WR_EN input is now a per-data-bit enable signal
265 - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
266 - Renamed ports of $lut cells (from I->O to A->Y)
267 - Renamed $_INV_ to $_NOT_
269 * Changes for simple synthesis flows
270 - There is now a "synth" command with a recommended default script
271 - Many improvements in synthesis of arithmetic functions to gates
272 - Multipliers and adders with many operands are using carry-save adder trees
273 - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
274 - Various new high-level optimizations on RTL netlist
275 - Various improvements in FSM optimization
276 - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
278 * Changes in internal APIs and RTLIL
279 - Added log_id() and log_cell() helper functions
280 - Added function-like cell creation helpers
281 - Added GetSize() function (like .size() but with int)
282 - Major refactoring of RTLIL::Module and related classes
283 - Major refactoring of RTLIL::SigSpec and related classes
284 - Now RTLIL::IdString is essentially an int
285 - Added macros for code coverage counters
286 - Added some Makefile magic for pretty make logs
287 - Added "kernel/yosys.h" with all the core definitions
288 - Changed a lot of code from FILE* to c++ streams
289 - Added RTLIL::Monitor API and "trace" command
290 - Added "Yosys" C++ namespace
292 * Changes relevant to SAT solving
293 - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
294 - Added native ezSAT support for vector shift ops
295 - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
297 * New commands (or large improvements to commands)
298 - Added "synth" command with default script
299 - Added "share" (finally some real resource sharing)
300 - Added "memory_share" (reduce number of ports on memories)
301 - Added "wreduce" and "alumacc" commands
302 - Added "opt -keepdc -fine -full -fast"
303 - Added some "test_*" commands
305 * Various other changes
306 - Added %D and %c select operators
307 - Added support for labels in yosys scripts
308 - Added support for here-documents in yosys scripts
309 - Support "+/" prefix for files from proc_share_dir
310 - Added "autoidx" statement to ilang language
311 - Switched from "yosys-svgviewer" to "xdot"
312 - Renamed "stdcells.v" to "techmap.v"
313 - Various bug fixes and small improvements
314 - Improved welcome and bye messages
317 Yosys 0.2.0 .. Yosys 0.3.0
318 --------------------------
320 * Driver program and overall behavior:
321 - Added "design -push" and "design -pop"
322 - Added "tee" command for redirecting log output
324 * Changes in the internal cell library:
325 - Added $dlatchsr and $_DLATCHSR_???_ cell types
327 * Improvements in Verilog frontend:
328 - Improved support for const functions (case, always, repeat)
329 - The generate..endgenerate keywords are now optional
330 - Added support for arrays of module instances
331 - Added support for "`default_nettype" directive
332 - Added support for "`line" directive
334 * Other front- and back-ends:
335 - Various changes to "write_blif" options
336 - Various improvements in EDIF backend
337 - Added "vhdl2verilog" pseudo-front-end
338 - Added "verific" pseudo-front-end
340 * Improvements in technology mapping:
341 - Added support for recursive techmap
342 - Added CONSTMSK and CONSTVAL features to techmap
343 - Added _TECHMAP_CONNMAP_*_ feature to techmap
344 - Added _TECHMAP_REPLACE_ feature to techmap
345 - Added "connwrappers" command for wrap-extract-unwrap method
346 - Added "extract -map %<design_name>" feature
347 - Added "extract -ignore_param ..." and "extract -ignore_parameters"
348 - Added "techmap -max_iter" option
350 * Improvements to "eval" and "sat" framework:
351 - Now include a copy of Minisat (with build fixes applied)
352 - Switched to Minisat::SimpSolver as SAT back-end
353 - Added "sat -dump_vcd" feature
354 - Added "sat -dump_cnf" feature
355 - Added "sat -initsteps <N>" feature
356 - Added "freduce -stop <N>" feature
357 - Added "freduce -dump <prefix>" feature
359 * Integration with ABC:
360 - Updated ABC rev to 7600ffb9340c
362 * Improvements in the internal APIs:
363 - Added RTLIL::Module::add... helper methods
364 - Various build fixes for OSX (Darwin) and OpenBSD
367 Yosys 0.1.0 .. Yosys 0.2.0
368 --------------------------
370 * Changes to the driver program:
371 - Added "yosys -h" and "yosys -H"
372 - Added support for backslash line continuation in scripts
373 - Added support for #-comments in same line as command
374 - Added "echo" and "log" commands
376 * Improvements in Verilog frontend:
377 - Added support for local registers in named blocks
378 - Added support for "case" in "generate" blocks
379 - Added support for $clog2 system function
380 - Added support for basic SystemVerilog assert statements
381 - Added preprocessor support for macro arguments
382 - Added preprocessor support for `elsif statement
383 - Added "verilog_defaults" command
384 - Added read_verilog -icells option
385 - Added support for constant sizes from parameters
386 - Added "read_verilog -setattr"
387 - Added support for function returning 'integer'
388 - Added limited support for function calls in parameter values
389 - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
391 * Other front- and back-ends:
393 - Added Liberty frontend
395 * Improvements in technology mapping:
396 - The "dfflibmap" command now strongly prefers solutions with
397 no inverters in clock paths
398 - The "dfflibmap" command now prefers cells with smaller area
399 - Added support for multiple -map options to techmap
400 - Added "dfflibmap" support for //-comments in liberty files
401 - Added "memory_unpack" command to revert "memory_collect"
402 - Added standard techmap rule "techmap -share_map pmux2mux.v"
403 - Added "iopadmap -bits"
404 - Added "setundef" command
405 - Added "hilomap" command
407 * Changes in the internal cell library:
408 - Major rewrite of simlib.v for better compatibility with other tools
409 - Added PRIORITY parameter to $memwr cells
410 - Added TRANSPARENT parameter to $memrd cells
411 - Added RD_TRANSPARENT parameter to $mem cells
412 - Added $bu0 cell (always 0-extend, even undef MSB)
413 - Added $assert cell type
414 - Added $slice and $concat cell types
416 * Integration with ABC:
417 - Updated ABC to hg rev 2058c8ccea68
418 - Tighter integration of ABC build with Yosys build. The make
419 targets 'make abc' and 'make install-abc' are now obsolete.
420 - Added support for passing FFs from one clock domain through ABC
421 - Now always use BLIF as exchange format with ABC
422 - Added support for "abc -script +<command_sequence>"
423 - Improved standard ABC recipe
424 - Added support for "keep" attribute to abc command
425 - Added "abc -dff / -clk / -keepff" options
427 * Improvements to "eval" and "sat" framework:
428 - Added support for "0" and "~0" in right-hand side -set expressions
429 - Added "eval -set-undef" and "eval -table"
430 - Added "sat -set-init" and "sat -set-init-*" for sequential problems
431 - Added undef support to SAT solver, incl. various new "sat" options
432 - Added correct support for === and !== for "eval" and "sat"
433 - Added "sat -tempinduct" (default -seq is now non-induction sequential)
434 - Added "sat -prove-asserts"
435 - Complete rewrite of the 'freduce' command
436 - Added "miter" command
437 - Added "sat -show-inputs" and "sat -show-outputs"
438 - Added "sat -ignore_unknown_cells" (now produce an error by default)
439 - Added "sat -falsify"
440 - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
441 - Added "expose" command
442 - Added support for @<sel_name> to sat and eval signal expressions
444 * Changes in the 'make test' framework and auxiliary test tools:
445 - Added autotest.sh -p and -f options
446 - Replaced autotest.sh ISIM support with XSIM support
447 - Added test cases for SAT framework
449 * Added "abbreviated IDs":
450 - Now $<something>$foo can be abbreviated as $foo.
451 - Usually this last part is a unique id (from RTLIL::autoidx)
452 - This abbreviated IDs are now also used in "show" output
454 * Other changes to selection framework:
455 - Now */ is optional in */<mode>:<arg> expressions
456 - Added "select -assert-none" and "select -assert-any"
457 - Added support for matching modules by attribute (A:<expr>)
458 - Added "select -none"
459 - Added support for r:<expr> pattern for matching cell parameters
460 - Added support for !=, <, <=, >=, > for attribute and parameter matching
461 - Added support for %s for selecting sub-modules
462 - Added support for %m for expanding selections to whole modules
463 - Added support for i:*, o:* and x:* pattern for selecting module ports
464 - Added support for s:<expr> pattern for matching wire width
465 - Added support for %a operation to select wire aliases
467 * Various other changes to commands and options:
468 - The "ls" command now supports wildcards
469 - Added "show -pause" and "show -format dot"
470 - Added "show -color" support for cells
471 - Added "show -label" and "show -notitle"
472 - Added "dump -m" and "dump -n"
473 - Added "history" command
474 - Added "rename -hide"
475 - Added "connect" command
476 - Added "splitnets -driver"
477 - Added "opt_const -mux_undef"
478 - Added "opt_const -mux_bool"
479 - Added "opt_const -undriven"
480 - Added "opt -mux_undef -mux_bool -undriven -purge"
481 - Added "hierarchy -libdir"
482 - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
483 - Added "delete" command
484 - Added "dump -append"
485 - Added "setattr" and "setparam" commands
486 - Added "design -stash/-copy-from/-copy-to"
487 - Added "copy" command
488 - Added "splice" command