CHANGELOG

   1
   2 List of major changes and improvements between releases
   3 =======================================================
   4
   5
   6 Yosys 0.8 .. Yosys 0.8-dev
   7 --------------------------
   8
   9  * Various
  10     - Added $changed support to read_verilog
  11     - Added "write_edif -attrprop"
  12     - Added "ice40_unlut" pass
  13     - Added "opt_lut" pass
  14     - Added "synth_ice40 -relut"
  15     - Added "synth_ice40 -noabc"
  16     - Added "gate2lut.v" techmap rule
  17     - Added "rename -src"
  18     - Added "equiv_opt" pass
  19     - Added "read_aiger" frontend
  20     - Added "muxpack" pass
  21     - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
  22     - "synth_xilinx" to now infer wide multiplexers
  23
  24
  25 Yosys 0.7 .. Yosys 0.8
  26 ----------------------
  27
  28  * Various
  29     - Many bugfixes and small improvements
  30     - Strip debug symbols from installed binary
  31     - Replace -ignore_redef with -[no]overwrite in front-ends
  32     - Added write_verilog hex dump support, add -nohex option
  33     - Added "write_verilog -decimal"
  34     - Added "scc -set_attr"
  35     - Added "verilog_defines" command
  36     - Remeber defines from one read_verilog to next
  37     - Added support for hierarchical defparam
  38     - Added FIRRTL back-end
  39     - Improved ABC default scripts
  40     - Added "design -reset-vlog"
  41     - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
  42     - Added Verilog $rtoi and $itor support
  43     - Added "check -initdrv"
  44     - Added "read_blif -wideports"
  45     - Added support for systemVerilog "++" and "--" operators
  46     - Added support for SystemVerilog unique, unique0, and priority case
  47     - Added "write_edif" options for edif "flavors"
  48     - Added support for resetall compiler directive
  49     - Added simple C beck-end (bitwise combinatorical only atm)
  50     - Added $_ANDNOT_ and $_ORNOT_ cell types
  51     - Added cell library aliases to "abc -g"
  52     - Added "setundef -anyseq"
  53     - Added "chtype" command
  54     - Added "design -import"
  55     - Added "write_table" command
  56     - Added "read_json" command
  57     - Added "sim" command
  58     - Added "extract_fa" and "extract_reduce" commands
  59     - Added "extract_counter" command
  60     - Added "opt_demorgan" command
  61     - Added support for $size and $bits SystemVerilog functions
  62     - Added "blackbox" command
  63     - Added "ltp" command
  64     - Added support for editline as replacement for readline
  65     - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
  66     - Added "yosys -E" for creating Makefile dependencies files
  67     - Added "synth -noshare"
  68     - Added "memory_nordff"
  69     - Added "setundef -undef -expose -anyconst"
  70     - Added "expose -input"
  71     - Added specify/specparam parser support (simply ignore them)
  72     - Added "write_blif -inames -iattr"
  73     - Added "hierarchy -simcheck"
  74     - Added an option to statically link abc into yosys
  75     - Added protobuf back-end
  76     - Added BLIF parsing support for .conn and .cname
  77     - Added read_verilog error checking for reg/wire/logic misuse
  78     - Added "make coverage" and ENABLE_GCOV build option
  79
  80  * Changes in Yosys APIs
  81     - Added ConstEval defaultval feature
  82     - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
  83     - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
  84     - Added log_file_warning() and log_file_error() functions
  85
  86  * Formal Verification
  87     - Added "write_aiger"
  88     - Added "yosys-smtbmc --aig"
  89     - Added "always <positive_int>" to .smtc format
  90     - Added $cover cell type and support for cover properties
  91     - Added $fair/$live cell type and support for liveness properties
  92     - Added smtbmc support for memory vcd dumping
  93     - Added "chformal" command
  94     - Added "write_smt2 -stbv" and "write_smt2 -stdt"
  95     - Fix equiv_simple, old behavior now available with "equiv_simple -short"
  96     - Change to Yices2 as default SMT solver (it is GPL now)
  97     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
  98     - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
  99     - Added a brand new "write_btor" command for BTOR2
 100     - Added clk2fflogic memory support and other improvements
 101     - Added "async memory write" support to write_smt2
 102     - Simulate clock toggling in yosys-smtbmc VCD output
 103     - Added $allseq/$allconst cells for EA-solving
 104     - Make -nordff the default in "prep"
 105     - Added (* gclk *) attribute
 106     - Added "async2sync" pass for single-clock designs with async resets
 107
 108  * Verific support
 109     - Many improvements in Verific front-end
 110     - Added proper handling of concurent SVA properties
 111     - Map "const" and "rand const" to $anyseq/$anyconst
 112     - Added "verific -import -flatten" and "verific -import -extnets"
 113     - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
 114     - Remove PSL support (because PSL has been removed in upstream Verific)
 115     - Improve integration with "hierarchy" command design elaboration
 116     - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
 117     - Added simpilied "read" command that automatically uses verific if available
 118     - Added "verific -set-<severity> <msg_id>.."
 119     - Added "verific -work <libname>"
 120
 121  * New back-ends
 122     - Added initial Coolrunner-II support
 123     - Added initial eASIC support
 124     - Added initial ECP5 support
 125
 126  * GreenPAK Support
 127     - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
 128
 129  * iCE40 Support
 130     - Add "synth_ice40 -vpr"
 131     - Add "synth_ice40 -nodffe"
 132     - Add "synth_ice40 -json"
 133     - Add Support for UltraPlus cells
 134
 135  * MAX10 and Cyclone IV Support
 136     - Added initial version of metacommand "synth_intel".
 137     - Improved write_verilog command to produce VQM netlist for Quartus Prime.
 138     - Added support for MAX10 FPGA family synthesis.
 139     - Added support for Cyclone IV family synthesis.
 140     - Added example of implementation for DE2i-150 board.
 141     - Added example of implementation for MAX10 development kit.
 142     - Added LFSR example from Asic World.
 143     - Added "dffinit -highlow" for mapping to Intel primitives
 144
 145
 146 Yosys 0.6 .. Yosys 0.7
 147 ----------------------
 148
 149  * Various
 150     - Added "yosys -D" feature
 151     - Added support for installed plugins in $(DATDIR)/plugins/
 152     - Renamed opt_const to opt_expr
 153     - Renamed opt_share to opt_merge
 154     - Added "prep -flatten" and "synth -flatten"
 155     - Added "prep -auto-top" and "synth -auto-top"
 156     - Using "mfs" and "lutpack" in ABC lut mapping
 157     - Support for abstract modules in chparam
 158     - Cleanup abstract modules at end of "hierarchy -top"
 159     - Added tristate buffer support to iopadmap
 160     - Added opt_expr support for div/mod by power-of-two
 161     - Added "select -assert-min <N> -assert-max <N>"
 162     - Added "attrmvcp" pass
 163     - Added "attrmap" command
 164     - Added "tee +INT -INT"
 165     - Added "zinit" pass
 166     - Added "setparam -type"
 167     - Added "shregmap" pass
 168     - Added "setundef -init"
 169     - Added "nlutmap -assert"
 170     - Added $sop cell type and "abc -sop -I <num> -P <num>"
 171     - Added "dc2" to default ABC scripts
 172     - Added "deminout"
 173     - Added "insbuf" command
 174     - Added "prep -nomem"
 175     - Added "opt_rmdff -keepdc"
 176     - Added "prep -nokeepdc"
 177     - Added initial version of "synth_gowin"
 178     - Added "fsm_expand -full"
 179     - Added support for fsm_encoding="user"
 180     - Many improvements in GreenPAK4 support
 181     - Added black box modules for all Xilinx 7-series lib cells
 182     - Added synth_ice40 support for latches via logic loops
 183     - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
 184
 185  * Build System
 186     - Added ABCEXTERNAL and ABCURL make variables
 187     - Added BINDIR, LIBDIR, and DATDIR make variables
 188     - Added PKG_CONFIG make variable
 189     - Added SEED make variable (for "make test")
 190     - Added YOSYS_VER_STR make variable
 191     - Updated min GCC requirement to GCC 4.8
 192     - Updated required Bison version to Bison 3.x
 193
 194  * Internal APIs
 195     - Added ast.h to exported headers
 196     - Added ScriptPass helper class for script-like passes
 197     - Added CellEdgesDatabase API
 198
 199  * Front-ends and Back-ends
 200     - Added filename glob support to all front-ends
 201     - Added avail (black-box) module params to ilang format
 202     - Added $display %m support
 203     - Added support for $stop Verilog system task
 204     - Added support for SystemVerilog packages
 205     - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
 206     - Added support for "active high" and "active low" latches in read_blif and write_blif
 207     - Use init value "2" for all uninitialized FFs in BLIF back-end
 208     - Added "read_blif -sop"
 209     - Added "write_blif -noalias"
 210     - Added various write_blif options for VTR support
 211     - write_json: also write module attributes.
 212     - Added "write_verilog -nodec -nostr -defparam"
 213     - Added "read_verilog -norestrict -assume-asserts"
 214     - Added support for bus interfaces to "read_liberty -lib"
 215     - Added liberty parser support for types within cell decls
 216     - Added "write_verilog -renameprefix -v"
 217     - Added "write_edif -nogndvcc"
 218
 219  * Formal Verification
 220     - Support for hierarchical designs in smt2 back-end
 221     - Yosys-smtbmc: Support for hierarchical VCD dumping
 222     - Added $initstate cell type and vlog function
 223     - Added $anyconst and $anyseq cell types and vlog functions
 224     - Added printing of code loc of failed asserts to yosys-smtbmc
 225     - Added memory_memx pass, "memory -memx", and "prep -memx"
 226     - Added "proc_mux -ifx"
 227     - Added "yosys-smtbmc -g"
 228     - Deprecated "write_smt2 -regs" (by default on now)
 229     - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
 230     - Added support for memories to smtio.py
 231     - Added "yosys-smtbmc --dump-vlogtb"
 232     - Added "yosys-smtbmc --smtc --dump-smtc"
 233     - Added "yosys-smtbmc --dump-all"
 234     - Added assertpmux command
 235     - Added "yosys-smtbmc --unroll"
 236     - Added $past, $stable, $rose, $fell SVA functions
 237     - Added "yosys-smtbmc --noinfo and --dummy"
 238     - Added "yosys-smtbmc --noincr"
 239     - Added "yosys-smtbmc --cex <filename>"
 240     - Added $ff and $_FF_ cell types
 241     - Added $global_clock verilog syntax support for creating $ff cells
 242     - Added clk2fflogic
 243
 244
 245 Yosys 0.5 .. Yosys 0.6
 246 ----------------------
 247
 248  * Various
 249      - Added Contributor Covenant Code of Conduct
 250      - Various improvements in dict<> and pool<>
 251      - Added hashlib::mfp and refactored SigMap
 252      - Improved support for reals as module parameters
 253      - Various improvements in SMT2 back-end
 254      - Added "keep_hierarchy" attribute
 255      - Verilog front-end: define `BLACKBOX in -lib mode
 256      - Added API for converting internal cells to AIGs
 257      - Added ENABLE_LIBYOSYS Makefile option
 258      - Removed "techmap -share_map" (use "-map +/filename" instead)
 259      - Switched all Python scripts to Python 3
 260      - Added support for $display()/$write() and $finish() to Verilog front-end
 261      - Added "yosys-smtbmc" formal verification flow
 262      - Added options for clang sanitizers to Makefile
 263
 264  * New commands and options
 265      - Added "scc -expect <N> -nofeedback"
 266      - Added "proc_dlatch"
 267      - Added "check"
 268      - Added "select %xe %cie %coe %M %C %R"
 269      - Added "sat -dump_json" (WaveJSON format)
 270      - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
 271      - Added "sat -stepsize" and "sat -tempinduct-step"
 272      - Added "sat -show-regs -show-public -show-all"
 273      - Added "write_json" (Native Yosys JSON format)
 274      - Added "write_blif -attr"
 275      - Added "dffinit"
 276      - Added "chparam"
 277      - Added "muxcover"
 278      - Added "pmuxtree"
 279      - Added memory_bram "make_outreg" feature
 280      - Added "splice -wires"
 281      - Added "dff2dffe -direct-match"
 282      - Added simplemap $lut support
 283      - Added "read_blif"
 284      - Added "opt_share -share_all"
 285      - Added "aigmap"
 286      - Added "write_smt2 -mem -regs -wires"
 287      - Added "memory -nordff"
 288      - Added "write_smv"
 289      - Added "synth -nordff -noalumacc"
 290      - Added "rename -top new_name"
 291      - Added "opt_const -clkinv"
 292      - Added "synth -nofsm"
 293      - Added "miter -assert"
 294      - Added "read_verilog -noautowire"
 295      - Added "read_verilog -nodpi"
 296      - Added "tribuf"
 297      - Added "lut2mux"
 298      - Added "nlutmap"
 299      - Added "qwp"
 300      - Added "test_cell -noeval"
 301      - Added "edgetypes"
 302      - Added "equiv_struct"
 303      - Added "equiv_purge"
 304      - Added "equiv_mark"
 305      - Added "equiv_add -try -cell"
 306      - Added "singleton"
 307      - Added "abc -g -luts"
 308      - Added "torder"
 309      - Added "write_blif -cname"
 310      - Added "submod -copy"
 311      - Added "dffsr2dff"
 312      - Added "stat -liberty"
 313
 314  * Synthesis metacommands
 315      - Various improvements in synth_xilinx
 316      - Added synth_ice40 and synth_greenpak4
 317      - Added "prep" metacommand for "synthesis lite"
 318
 319  * Cell library changes
 320      - Added cell types to "help" system
 321      - Added $meminit cell type
 322      - Added $assume cell type
 323      - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
 324      - Added $tribuf and $_TBUF_ cell types
 325      - Added read-enable to memory model
 326
 327  * YosysJS
 328      - Various improvements in emscripten build
 329      - Added alternative webworker-based JS API
 330      - Added a few example applications
 331
 332
 333 Yosys 0.4 .. Yosys 0.5
 334 ----------------------
 335
 336  * API changes
 337      - Added log_warning()
 338      - Added eval_select_args() and eval_select_op()
 339      - Added cell->known(), cell->input(portname), cell->output(portname)
 340      - Skip blackbox modules in design->selected_modules()
 341      - Replaced std::map<> and std::set<> with dict<> and pool<>
 342      - New SigSpec::extend() is what used to be SigSpec::extend_u0()
 343      - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
 344
 345  * Cell library changes
 346      - Added flip-flops with enable ($dffe etc.)
 347      - Added $equiv cells for equivalence checking framework
 348
 349  * Various
 350      - Updated ABC to hg rev 61ad5f908c03
 351      - Added clock domain partitioning to ABC pass
 352      - Improved plugin building (see "yosys-config --build")
 353      - Added ENABLE_NDEBUG Makefile flag for high-performance builds
 354      - Added "yosys -d", "yosys -L" and other driver improvements
 355      - Added support for multi-bit (array) cell ports to "write_edif"
 356      - Now printing most output to stdout, not stderr
 357      - Added "onehot" attribute (set by "fsm_map")
 358      - Various performance improvements
 359      - Vastly improved Xilinx flow
 360      - Added "make unsintall"
 361
 362  * Equivalence checking
 363      - Added equivalence checking commands:
 364          equiv_make equiv_simple equiv_status
 365          equiv_induct equiv_miter
 366          equiv_add equiv_remove
 367
 368  * Block RAM support:
 369      - Added "memory_bram" command
 370      - Added BRAM support to Xilinx flow
 371
 372  * Other New Commands and Options
 373      - Added "dff2dffe"
 374      - Added "fsm -encfile"
 375      - Added "dfflibmap -prepare"
 376      - Added "write_blid -unbuf -undef -blackbox"
 377      - Added "write_smt2" for writing SMT-LIBv2 files
 378      - Added "test_cell -w -muxdiv"
 379      - Added "select -read"
 380
 381
 382 Yosys 0.3.0 .. Yosys 0.4
 383 ------------------------
 384
 385  * Platform Support
 386      - Added support for mxe-based cross-builds for win32
 387      - Added sourcecode-export as VisualStudio project
 388      - Added experimental EMCC (JavaScript) support
 389
 390  * Verilog Frontend
 391      - Added -sv option for SystemVerilog (and automatic *.sv file support)
 392      - Added support for real-valued constants and constant expressions
 393      - Added support for non-standard "via_celltype" attribute on task/func
 394      - Added support for non-standard "module mod_name(...);" syntax
 395      - Added support for non-standard """ macro bodies
 396      - Added support for array with more than one dimension
 397      - Added support for $readmemh and $readmemb
 398      - Added support for DPI functions
 399
 400  * Changes in internal cell library
 401      - Added $shift and $shiftx cell types
 402      - Added $alu, $lcu, $fa and $macc cell types
 403      - Removed $bu0 and $safe_pmux cell types
 404      - $mem/$memwr WR_EN input is now a per-data-bit enable signal
 405      - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
 406      - Renamed ports of $lut cells (from I->O to A->Y)
 407      - Renamed $_INV_ to $_NOT_
 408
 409  * Changes for simple synthesis flows
 410      - There is now a "synth" command with a recommended default script
 411      - Many improvements in synthesis of arithmetic functions to gates
 412          - Multipliers and adders with many operands are using carry-save adder trees
 413          - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
 414      - Various new high-level optimizations on RTL netlist
 415      - Various improvements in FSM optimization
 416      - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
 417
 418  * Changes in internal APIs and RTLIL
 419      - Added log_id() and log_cell() helper functions
 420      - Added function-like cell creation helpers
 421      - Added GetSize() function (like .size() but with int)
 422      - Major refactoring of RTLIL::Module and related classes
 423      - Major refactoring of RTLIL::SigSpec and related classes
 424      - Now RTLIL::IdString is essentially an int
 425      - Added macros for code coverage counters
 426      - Added some Makefile magic for pretty make logs
 427      - Added "kernel/yosys.h" with all the core definitions
 428      - Changed a lot of code from FILE* to c++ streams
 429      - Added RTLIL::Monitor API and "trace" command
 430      - Added "Yosys" C++ namespace
 431
 432  * Changes relevant to SAT solving
 433      - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
 434      - Added native ezSAT support for vector shift ops
 435      - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
 436
 437  * New commands (or large improvements to commands)
 438      - Added "synth" command with default script
 439      - Added "share" (finally some real resource sharing)
 440      - Added "memory_share" (reduce number of ports on memories)
 441      - Added "wreduce" and "alumacc" commands
 442      - Added "opt -keepdc -fine -full -fast"
 443      - Added some "test_*" commands
 444
 445  * Various other changes
 446      - Added %D and %c select operators
 447      - Added support for labels in yosys scripts
 448      - Added support for here-documents in yosys scripts
 449      - Support "+/" prefix for files from proc_share_dir
 450      - Added "autoidx" statement to ilang language
 451      - Switched from "yosys-svgviewer" to "xdot"
 452      - Renamed "stdcells.v" to "techmap.v"
 453      - Various bug fixes and small improvements
 454      - Improved welcome and bye messages
 455
 456
 457 Yosys 0.2.0 .. Yosys 0.3.0
 458 --------------------------
 459
 460  * Driver program and overall behavior:
 461      - Added "design -push" and "design -pop"
 462      - Added "tee" command for redirecting log output
 463
 464  * Changes in the internal cell library:
 465      - Added $dlatchsr and $_DLATCHSR_???_ cell types
 466
 467  * Improvements in Verilog frontend:
 468      - Improved support for const functions (case, always, repeat)
 469      - The generate..endgenerate keywords are now optional
 470      - Added support for arrays of module instances
 471      - Added support for "`default_nettype" directive
 472      - Added support for "`line" directive
 473
 474  * Other front- and back-ends:
 475      - Various changes to "write_blif" options
 476      - Various improvements in EDIF backend
 477      - Added "vhdl2verilog" pseudo-front-end
 478      - Added "verific" pseudo-front-end
 479
 480  * Improvements in technology mapping:
 481      - Added support for recursive techmap
 482      - Added CONSTMSK and CONSTVAL features to techmap
 483      - Added _TECHMAP_CONNMAP_*_ feature to techmap
 484      - Added _TECHMAP_REPLACE_ feature to techmap
 485      - Added "connwrappers" command for wrap-extract-unwrap method
 486      - Added "extract -map %<design_name>" feature
 487      - Added "extract -ignore_param ..." and "extract -ignore_parameters"
 488      - Added "techmap -max_iter" option
 489
 490  * Improvements to "eval" and "sat" framework:
 491      - Now include a copy of Minisat (with build fixes applied)
 492      - Switched to Minisat::SimpSolver as SAT back-end
 493      - Added "sat -dump_vcd" feature
 494      - Added "sat -dump_cnf" feature
 495      - Added "sat -initsteps <N>" feature
 496      - Added "freduce -stop <N>" feature
 497      - Added "freduce -dump <prefix>" feature
 498
 499  * Integration with ABC:
 500      - Updated ABC rev to 7600ffb9340c
 501
 502  * Improvements in the internal APIs:
 503      - Added RTLIL::Module::add... helper methods
 504      - Various build fixes for OSX (Darwin) and OpenBSD
 505
 506
 507 Yosys 0.1.0 .. Yosys 0.2.0
 508 --------------------------
 509
 510  * Changes to the driver program:
 511      - Added "yosys -h" and "yosys -H"
 512      - Added support for backslash line continuation in scripts
 513      - Added support for #-comments in same line as command
 514      - Added "echo" and "log" commands
 515
 516  * Improvements in Verilog frontend:
 517      - Added support for local registers in named blocks
 518      - Added support for "case" in "generate" blocks
 519      - Added support for $clog2 system function
 520      - Added support for basic SystemVerilog assert statements
 521      - Added preprocessor support for macro arguments
 522      - Added preprocessor support for `elsif statement
 523      - Added "verilog_defaults" command
 524      - Added read_verilog -icells option
 525      - Added support for constant sizes from parameters
 526      - Added "read_verilog -setattr"
 527      - Added support for function returning 'integer'
 528      - Added limited support for function calls in parameter values
 529      - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
 530
 531  * Other front- and back-ends:
 532      - Added BTOR backend
 533      - Added Liberty frontend
 534
 535  * Improvements in technology mapping:
 536      - The "dfflibmap" command now strongly prefers solutions with
 537            no inverters in clock paths
 538      - The "dfflibmap" command now prefers cells with smaller area
 539      - Added support for multiple -map options to techmap
 540      - Added "dfflibmap" support for //-comments in liberty files
 541      - Added "memory_unpack" command to revert "memory_collect"
 542      - Added standard techmap rule "techmap -share_map pmux2mux.v"
 543      - Added "iopadmap -bits"
 544      - Added "setundef" command
 545      - Added "hilomap" command
 546
 547  * Changes in the internal cell library:
 548      - Major rewrite of simlib.v for better compatibility with other tools
 549      - Added PRIORITY parameter to $memwr cells
 550      - Added TRANSPARENT parameter to $memrd cells
 551      - Added RD_TRANSPARENT parameter to $mem cells
 552      - Added $bu0 cell (always 0-extend, even undef MSB)
 553      - Added $assert cell type
 554      - Added $slice and $concat cell types
 555
 556  * Integration with ABC:
 557      - Updated ABC to hg rev 2058c8ccea68
 558      - Tighter integration of ABC build with Yosys build. The make
 559            targets 'make abc' and 'make install-abc' are now obsolete.
 560      - Added support for passing FFs from one clock domain through ABC
 561      - Now always use BLIF as exchange format with ABC
 562      - Added support for "abc -script +<command_sequence>"
 563      - Improved standard ABC recipe
 564      - Added support for "keep" attribute to abc command
 565      - Added "abc -dff / -clk / -keepff" options
 566
 567  * Improvements to "eval" and "sat" framework:
 568      - Added support for "0" and "~0" in right-hand side -set expressions
 569      - Added "eval -set-undef" and "eval -table"
 570      - Added "sat -set-init" and "sat -set-init-*" for sequential problems
 571      - Added undef support to SAT solver, incl. various new "sat" options
 572      - Added correct support for === and !== for "eval" and "sat"
 573      - Added "sat -tempinduct" (default -seq is now non-induction sequential)
 574      - Added "sat -prove-asserts"
 575      - Complete rewrite of the 'freduce' command
 576      - Added "miter" command
 577      - Added "sat -show-inputs" and "sat -show-outputs"
 578      - Added "sat -ignore_unknown_cells" (now produce an error by default)
 579      - Added "sat -falsify"
 580      - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
 581      - Added "expose" command
 582      - Added support for @<sel_name> to sat and eval signal expressions
 583
 584  * Changes in the 'make test' framework and auxiliary test tools:
 585      - Added autotest.sh -p and -f options
 586      - Replaced autotest.sh ISIM support with XSIM support
 587      - Added test cases for SAT framework
 588
 589  * Added "abbreviated IDs":
 590      - Now $<something>$foo can be abbreviated as $foo.
 591      - Usually this last part is a unique id (from RTLIL::autoidx)
 592      - This abbreviated IDs are now also used in "show" output
 593
 594  * Other changes to selection framework:
 595      - Now */ is optional in */<mode>:<arg> expressions
 596      - Added "select -assert-none" and "select -assert-any"
 597      - Added support for matching modules by attribute (A:<expr>)
 598      - Added "select -none"
 599      - Added support for r:<expr> pattern for matching cell parameters
 600      - Added support for !=, <, <=, >=, > for attribute and parameter matching
 601      - Added support for %s for selecting sub-modules
 602      - Added support for %m for expanding selections to whole modules
 603      - Added support for i:*, o:* and x:* pattern for selecting module ports
 604      - Added support for s:<expr> pattern for matching wire width
 605      - Added support for %a operation to select wire aliases
 606
 607  * Various other changes to commands and options:
 608      - The "ls" command now supports wildcards
 609      - Added "show -pause" and "show -format dot"
 610      - Added "show -color" support for cells
 611      - Added "show -label" and "show -notitle"
 612      - Added "dump -m" and "dump -n"
 613      - Added "history" command
 614      - Added "rename -hide"
 615      - Added "connect" command
 616      - Added "splitnets -driver"
 617      - Added "opt_const -mux_undef"
 618      - Added "opt_const -mux_bool"
 619      - Added "opt_const -undriven"
 620      - Added "opt -mux_undef -mux_bool -undriven -purge"
 621      - Added "hierarchy -libdir"
 622      - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
 623      - Added "delete" command
 624      - Added "dump -append"
 625      - Added "setattr" and "setparam" commands
 626      - Added "design -stash/-copy-from/-copy-to"
 627      - Added "copy" command
 628      - Added "splice" command
 629