CHANGELOG

   1
   2 List of major changes and improvements between releases
   3 =======================================================
   4
   5
   6 Yosys 0.7 .. Yosys ???    (2017-12-12)
   7 ----------------------
   8
   9  * Various
  10     - Many bugfixes and small improvements
  11     - Added write_verilog hex dump support, add -nohex option
  12     - Added "write_verilog -decimal"
  13     - Added "scc -set_attr"
  14     - Added "verilog_defines" command
  15     - Remeber defines from one read_verilog to next
  16     - Added support for hierarchical defparam
  17     - Added FIRRTL back-end
  18     - Improved ABC default scripts
  19     - Added "design -reset-vlog"
  20     - Added "yosys -W regex" and "yosys -w regex"
  21     - Added Verilog $rtoi and $itor support
  22     - Added "check -initdrv"
  23     - Added "read_blif -wideports"
  24     - Added support for systemVerilog "++" and "--" operators
  25     - Added support for SystemVerilog unique, unique0, and priority case
  26     - Added "write_edif" options for edif "flavors"
  27     - Added support for resetall compiler directive
  28     - Added simple C beck-end (bitwise combinatorical only atm)
  29     - Added $_ANDNOT_ and $_ORNOT_ cell types
  30     - Added cell library aliases to "abc -g"
  31     - Added "setundef -anyseq"
  32     - Added "chtype" command
  33     - Added "design -import"
  34     - Added "write_table" command
  35     - Added "read_json" command
  36     - Added "sim" command
  37     - Added "extract_fa" and "extract_reduce" commands
  38     - Added "extract_counter" command
  39     - Added "opt_demorgan" command
  40     - Added support for $size and $bits SystemVerilog functions
  41     - Added "blackbox" command
  42     - Added "ltp" command
  43     - Added support for editline as replacement for readline
  44     - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
  45
  46  * Changes in Yosys APIs
  47     - Added ConstEval defaultval feature
  48     - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
  49
  50  * Formal Verification
  51     - Added "write_aiger"
  52     - Added "yosys-smtbmc --aig"
  53     - Added "always <positive_int>" to .smtc format
  54     - Added $cover cell type and support for cover properties
  55     - Added $fair/$live cell type and support for liveness properties
  56     - Added smtbmc support for memory vcd dumping
  57     - Added "chformal" command
  58     - Added "write_smt2 -stbv" and "write_smt2 -stdt"
  59     - Fix equiv_simple, old behavior now available with "equiv_simple -short"
  60     - Change to Yices2 as default SMT solver (it is GPL now)
  61     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
  62     - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
  63     - Added a brand new "write_btor" command for BTOR2
  64
  65  * Verific support
  66     - Many improvements in Verific front-end
  67     - Added proper handling of concurent SVA properties
  68     - Map "const" and "rand const" to $anyseq/$anyconst
  69     - Added "verific -import -flatten" and "verific -import -extnets"
  70     - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
  71     - Remove PSL support (because PSL has been removed in upstream Verific)
  72
  73  * New back-ends
  74     - Added initial Coolrunner-II support
  75     - Added initial eASIC support
  76
  77  * GreenPAK Support
  78     - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
  79
  80  * iCE40 Support
  81     - Add "synth_ice40 -vpr"
  82     - Add Support for UltraPlus cells
  83
  84  * MAX10 and Cyclone IV Support
  85     - Added initial version of metacommand "synth_intel".
  86     - Improved write_verilog command to produce VQM netlist for Quartus Prime.
  87     - Added support for MAX10 FPGA family synthesis.
  88     - Added support for Cyclone IV family synthesis.
  89     - Added example of implementation for DE2i-150 board.
  90     - Added example of implementation for MAX10 development kit.
  91     - Added LFSR example from Asic World.
  92
  93
  94 Yosys 0.6 .. Yosys 0.7
  95 ----------------------
  96
  97  * Various
  98     - Added "yosys -D" feature
  99     - Added support for installed plugins in $(DATDIR)/plugins/
 100     - Renamed opt_const to opt_expr
 101     - Renamed opt_share to opt_merge
 102     - Added "prep -flatten" and "synth -flatten"
 103     - Added "prep -auto-top" and "synth -auto-top"
 104     - Using "mfs" and "lutpack" in ABC lut mapping
 105     - Support for abstract modules in chparam
 106     - Cleanup abstract modules at end of "hierarchy -top"
 107     - Added tristate buffer support to iopadmap
 108     - Added opt_expr support for div/mod by power-of-two
 109     - Added "select -assert-min <N> -assert-max <N>"
 110     - Added "attrmvcp" pass
 111     - Added "attrmap" command
 112     - Added "tee +INT -INT"
 113     - Added "zinit" pass
 114     - Added "setparam -type"
 115     - Added "shregmap" pass
 116     - Added "setundef -init"
 117     - Added "nlutmap -assert"
 118     - Added $sop cell type and "abc -sop -I <num> -P <num>"
 119     - Added "dc2" to default ABC scripts
 120     - Added "deminout"
 121     - Added "insbuf" command
 122     - Added "prep -nomem"
 123     - Added "opt_rmdff -keepdc"
 124     - Added "prep -nokeepdc"
 125     - Added initial version of "synth_gowin"
 126     - Added "fsm_expand -full"
 127     - Added support for fsm_encoding="user"
 128     - Many improvements in GreenPAK4 support
 129     - Added black box modules for all Xilinx 7-series lib cells
 130     - Added synth_ice40 support for latches via logic loops
 131     - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
 132
 133  * Build System
 134     - Added ABCEXTERNAL and ABCURL make variables
 135     - Added BINDIR, LIBDIR, and DATDIR make variables
 136     - Added PKG_CONFIG make variable
 137     - Added SEED make variable (for "make test")
 138     - Added YOSYS_VER_STR make variable
 139     - Updated min GCC requirement to GCC 4.8
 140     - Updated required Bison version to Bison 3.x
 141
 142  * Internal APIs
 143     - Added ast.h to exported headers
 144     - Added ScriptPass helper class for script-like passes
 145     - Added CellEdgesDatabase API
 146
 147  * Front-ends and Back-ends
 148     - Added filename glob support to all front-ends
 149     - Added avail (black-box) module params to ilang format
 150     - Added $display %m support
 151     - Added support for $stop Verilog system task
 152     - Added support for SystemVerilog packages
 153     - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
 154     - Added support for "active high" and "active low" latches in read_blif and write_blif
 155     - Use init value "2" for all uninitialized FFs in BLIF back-end
 156     - Added "read_blif -sop"
 157     - Added "write_blif -noalias"
 158     - Added various write_blif options for VTR support
 159     - write_json: also write module attributes.
 160     - Added "write_verilog -nodec -nostr -defparam"
 161     - Added "read_verilog -norestrict -assume-asserts"
 162     - Added support for bus interfaces to "read_liberty -lib"
 163     - Added liberty parser support for types within cell decls
 164     - Added "write_verilog -renameprefix -v"
 165     - Added "write_edif -nogndvcc"
 166
 167  * Formal Verification
 168     - Support for hierarchical designs in smt2 back-end
 169     - Yosys-smtbmc: Support for hierarchical VCD dumping
 170     - Added $initstate cell type and vlog function
 171     - Added $anyconst and $anyseq cell types and vlog functions
 172     - Added printing of code loc of failed asserts to yosys-smtbmc
 173     - Added memory_memx pass, "memory -memx", and "prep -memx"
 174     - Added "proc_mux -ifx"
 175     - Added "yosys-smtbmc -g"
 176     - Deprecated "write_smt2 -regs" (by default on now)
 177     - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
 178     - Added support for memories to smtio.py
 179     - Added "yosys-smtbmc --dump-vlogtb"
 180     - Added "yosys-smtbmc --smtc --dump-smtc"
 181     - Added "yosys-smtbmc --dump-all"
 182     - Added assertpmux command
 183     - Added "yosys-smtbmc --unroll"
 184     - Added $past, $stable, $rose, $fell SVA functions
 185     - Added "yosys-smtbmc --noinfo and --dummy"
 186     - Added "yosys-smtbmc --noincr"
 187     - Added "yosys-smtbmc --cex <filename>"
 188     - Added $ff and $_FF_ cell types
 189     - Added $global_clock verilog syntax support for creating $ff cells
 190     - Added clk2fflogic
 191
 192
 193 Yosys 0.5 .. Yosys 0.6
 194 ----------------------
 195
 196  * Various
 197      - Added Contributor Covenant Code of Conduct
 198      - Various improvements in dict<> and pool<>
 199      - Added hashlib::mfp and refactored SigMap
 200      - Improved support for reals as module parameters
 201      - Various improvements in SMT2 back-end
 202      - Added "keep_hierarchy" attribute
 203      - Verilog front-end: define `BLACKBOX in -lib mode
 204      - Added API for converting internal cells to AIGs
 205      - Added ENABLE_LIBYOSYS Makefile option
 206      - Removed "techmap -share_map" (use "-map +/filename" instead)
 207      - Switched all Python scripts to Python 3
 208      - Added support for $display()/$write() and $finish() to Verilog front-end
 209      - Added "yosys-smtbmc" formal verification flow
 210      - Added options for clang sanitizers to Makefile
 211
 212  * New commands and options
 213      - Added "scc -expect <N> -nofeedback"
 214      - Added "proc_dlatch"
 215      - Added "check"
 216      - Added "select %xe %cie %coe %M %C %R"
 217      - Added "sat -dump_json" (WaveJSON format)
 218      - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
 219      - Added "sat -stepsize" and "sat -tempinduct-step"
 220      - Added "sat -show-regs -show-public -show-all"
 221      - Added "write_json" (Native Yosys JSON format)
 222      - Added "write_blif -attr"
 223      - Added "dffinit"
 224      - Added "chparam"
 225      - Added "muxcover"
 226      - Added "pmuxtree"
 227      - Added memory_bram "make_outreg" feature
 228      - Added "splice -wires"
 229      - Added "dff2dffe -direct-match"
 230      - Added simplemap $lut support
 231      - Added "read_blif"
 232      - Added "opt_share -share_all"
 233      - Added "aigmap"
 234      - Added "write_smt2 -mem -regs -wires"
 235      - Added "memory -nordff"
 236      - Added "write_smv"
 237      - Added "synth -nordff -noalumacc"
 238      - Added "rename -top new_name"
 239      - Added "opt_const -clkinv"
 240      - Added "synth -nofsm"
 241      - Added "miter -assert"
 242      - Added "read_verilog -noautowire"
 243      - Added "read_verilog -nodpi"
 244      - Added "tribuf"
 245      - Added "lut2mux"
 246      - Added "nlutmap"
 247      - Added "qwp"
 248      - Added "test_cell -noeval"
 249      - Added "edgetypes"
 250      - Added "equiv_struct"
 251      - Added "equiv_purge"
 252      - Added "equiv_mark"
 253      - Added "equiv_add -try -cell"
 254      - Added "singleton"
 255      - Added "abc -g -luts"
 256      - Added "torder"
 257      - Added "write_blif -cname"
 258      - Added "submod -copy"
 259      - Added "dffsr2dff"
 260      - Added "stat -liberty"
 261
 262  * Synthesis metacommands
 263      - Various improvements in synth_xilinx
 264      - Added synth_ice40 and synth_greenpak4
 265      - Added "prep" metacommand for "synthesis lite"
 266
 267  * Cell library changes
 268      - Added cell types to "help" system
 269      - Added $meminit cell type
 270      - Added $assume cell type
 271      - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
 272      - Added $tribuf and $_TBUF_ cell types
 273      - Added read-enable to memory model
 274
 275  * YosysJS
 276      - Various improvements in emscripten build
 277      - Added alternative webworker-based JS API
 278      - Added a few example applications
 279
 280
 281 Yosys 0.4 .. Yosys 0.5
 282 ----------------------
 283
 284  * API changes
 285      - Added log_warning()
 286      - Added eval_select_args() and eval_select_op()
 287      - Added cell->known(), cell->input(portname), cell->output(portname)
 288      - Skip blackbox modules in design->selected_modules()
 289      - Replaced std::map<> and std::set<> with dict<> and pool<>
 290      - New SigSpec::extend() is what used to be SigSpec::extend_u0()
 291      - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
 292
 293  * Cell library changes
 294      - Added flip-flops with enable ($dffe etc.)
 295      - Added $equiv cells for equivalence checking framework
 296
 297  * Various
 298      - Updated ABC to hg rev 61ad5f908c03
 299      - Added clock domain partitioning to ABC pass
 300      - Improved plugin building (see "yosys-config --build")
 301      - Added ENABLE_NDEBUG Makefile flag for high-performance builds
 302      - Added "yosys -d", "yosys -L" and other driver improvements
 303      - Added support for multi-bit (array) cell ports to "write_edif"
 304      - Now printing most output to stdout, not stderr
 305      - Added "onehot" attribute (set by "fsm_map")
 306      - Various performance improvements
 307      - Vastly improved Xilinx flow
 308      - Added "make unsintall"
 309
 310  * Equivalence checking
 311      - Added equivalence checking commands:
 312          equiv_make equiv_simple equiv_status
 313          equiv_induct equiv_miter
 314          equiv_add equiv_remove
 315
 316  * Block RAM support:
 317      - Added "memory_bram" command
 318      - Added BRAM support to Xilinx flow
 319
 320  * Other New Commands and Options
 321      - Added "dff2dffe"
 322      - Added "fsm -encfile"
 323      - Added "dfflibmap -prepare"
 324      - Added "write_blid -unbuf -undef -blackbox"
 325      - Added "write_smt2" for writing SMT-LIBv2 files
 326      - Added "test_cell -w -muxdiv"
 327      - Added "select -read"
 328
 329
 330 Yosys 0.3.0 .. Yosys 0.4
 331 ------------------------
 332
 333  * Platform Support
 334      - Added support for mxe-based cross-builds for win32
 335      - Added sourcecode-export as VisualStudio project
 336      - Added experimental EMCC (JavaScript) support
 337
 338  * Verilog Frontend
 339      - Added -sv option for SystemVerilog (and automatic *.sv file support)
 340      - Added support for real-valued constants and constant expressions
 341      - Added support for non-standard "via_celltype" attribute on task/func
 342      - Added support for non-standard "module mod_name(...);" syntax
 343      - Added support for non-standard """ macro bodies
 344      - Added support for array with more than one dimension
 345      - Added support for $readmemh and $readmemb
 346      - Added support for DPI functions
 347
 348  * Changes in internal cell library
 349      - Added $shift and $shiftx cell types
 350      - Added $alu, $lcu, $fa and $macc cell types
 351      - Removed $bu0 and $safe_pmux cell types
 352      - $mem/$memwr WR_EN input is now a per-data-bit enable signal
 353      - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
 354      - Renamed ports of $lut cells (from I->O to A->Y)
 355      - Renamed $_INV_ to $_NOT_
 356
 357  * Changes for simple synthesis flows
 358      - There is now a "synth" command with a recommended default script
 359      - Many improvements in synthesis of arithmetic functions to gates
 360          - Multipliers and adders with many operands are using carry-save adder trees
 361          - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
 362      - Various new high-level optimizations on RTL netlist
 363      - Various improvements in FSM optimization
 364      - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
 365
 366  * Changes in internal APIs and RTLIL
 367      - Added log_id() and log_cell() helper functions
 368      - Added function-like cell creation helpers
 369      - Added GetSize() function (like .size() but with int)
 370      - Major refactoring of RTLIL::Module and related classes
 371      - Major refactoring of RTLIL::SigSpec and related classes
 372      - Now RTLIL::IdString is essentially an int
 373      - Added macros for code coverage counters
 374      - Added some Makefile magic for pretty make logs
 375      - Added "kernel/yosys.h" with all the core definitions
 376      - Changed a lot of code from FILE* to c++ streams
 377      - Added RTLIL::Monitor API and "trace" command
 378      - Added "Yosys" C++ namespace
 379
 380  * Changes relevant to SAT solving
 381      - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
 382      - Added native ezSAT support for vector shift ops
 383      - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
 384
 385  * New commands (or large improvements to commands)
 386      - Added "synth" command with default script
 387      - Added "share" (finally some real resource sharing)
 388      - Added "memory_share" (reduce number of ports on memories)
 389      - Added "wreduce" and "alumacc" commands
 390      - Added "opt -keepdc -fine -full -fast"
 391      - Added some "test_*" commands
 392
 393  * Various other changes
 394      - Added %D and %c select operators
 395      - Added support for labels in yosys scripts
 396      - Added support for here-documents in yosys scripts
 397      - Support "+/" prefix for files from proc_share_dir
 398      - Added "autoidx" statement to ilang language
 399      - Switched from "yosys-svgviewer" to "xdot"
 400      - Renamed "stdcells.v" to "techmap.v"
 401      - Various bug fixes and small improvements
 402      - Improved welcome and bye messages
 403
 404
 405 Yosys 0.2.0 .. Yosys 0.3.0
 406 --------------------------
 407
 408  * Driver program and overall behavior:
 409      - Added "design -push" and "design -pop"
 410      - Added "tee" command for redirecting log output
 411
 412  * Changes in the internal cell library:
 413      - Added $dlatchsr and $_DLATCHSR_???_ cell types
 414
 415  * Improvements in Verilog frontend:
 416      - Improved support for const functions (case, always, repeat)
 417      - The generate..endgenerate keywords are now optional
 418      - Added support for arrays of module instances
 419      - Added support for "`default_nettype" directive
 420      - Added support for "`line" directive
 421
 422  * Other front- and back-ends:
 423      - Various changes to "write_blif" options
 424      - Various improvements in EDIF backend
 425      - Added "vhdl2verilog" pseudo-front-end
 426      - Added "verific" pseudo-front-end
 427
 428  * Improvements in technology mapping:
 429      - Added support for recursive techmap
 430      - Added CONSTMSK and CONSTVAL features to techmap
 431      - Added _TECHMAP_CONNMAP_*_ feature to techmap
 432      - Added _TECHMAP_REPLACE_ feature to techmap
 433      - Added "connwrappers" command for wrap-extract-unwrap method
 434      - Added "extract -map %<design_name>" feature
 435      - Added "extract -ignore_param ..." and "extract -ignore_parameters"
 436      - Added "techmap -max_iter" option
 437
 438  * Improvements to "eval" and "sat" framework:
 439      - Now include a copy of Minisat (with build fixes applied)
 440      - Switched to Minisat::SimpSolver as SAT back-end
 441      - Added "sat -dump_vcd" feature
 442      - Added "sat -dump_cnf" feature
 443      - Added "sat -initsteps <N>" feature
 444      - Added "freduce -stop <N>" feature
 445      - Added "freduce -dump <prefix>" feature
 446
 447  * Integration with ABC:
 448      - Updated ABC rev to 7600ffb9340c
 449
 450  * Improvements in the internal APIs:
 451      - Added RTLIL::Module::add... helper methods
 452      - Various build fixes for OSX (Darwin) and OpenBSD
 453
 454
 455 Yosys 0.1.0 .. Yosys 0.2.0
 456 --------------------------
 457
 458  * Changes to the driver program:
 459      - Added "yosys -h" and "yosys -H"
 460      - Added support for backslash line continuation in scripts
 461      - Added support for #-comments in same line as command
 462      - Added "echo" and "log" commands
 463
 464  * Improvements in Verilog frontend:
 465      - Added support for local registers in named blocks
 466      - Added support for "case" in "generate" blocks
 467      - Added support for $clog2 system function
 468      - Added support for basic SystemVerilog assert statements
 469      - Added preprocessor support for macro arguments
 470      - Added preprocessor support for `elsif statement
 471      - Added "verilog_defaults" command
 472      - Added read_verilog -icells option
 473      - Added support for constant sizes from parameters
 474      - Added "read_verilog -setattr"
 475      - Added support for function returning 'integer'
 476      - Added limited support for function calls in parameter values
 477      - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
 478
 479  * Other front- and back-ends:
 480      - Added BTOR backend
 481      - Added Liberty frontend
 482
 483  * Improvements in technology mapping:
 484      - The "dfflibmap" command now strongly prefers solutions with
 485            no inverters in clock paths
 486      - The "dfflibmap" command now prefers cells with smaller area
 487      - Added support for multiple -map options to techmap
 488      - Added "dfflibmap" support for //-comments in liberty files
 489      - Added "memory_unpack" command to revert "memory_collect"
 490      - Added standard techmap rule "techmap -share_map pmux2mux.v"
 491      - Added "iopadmap -bits"
 492      - Added "setundef" command
 493      - Added "hilomap" command
 494
 495  * Changes in the internal cell library:
 496      - Major rewrite of simlib.v for better compatibility with other tools
 497      - Added PRIORITY parameter to $memwr cells
 498      - Added TRANSPARENT parameter to $memrd cells
 499      - Added RD_TRANSPARENT parameter to $mem cells
 500      - Added $bu0 cell (always 0-extend, even undef MSB)
 501      - Added $assert cell type
 502      - Added $slice and $concat cell types
 503
 504  * Integration with ABC:
 505      - Updated ABC to hg rev 2058c8ccea68
 506      - Tighter integration of ABC build with Yosys build. The make
 507            targets 'make abc' and 'make install-abc' are now obsolete.
 508      - Added support for passing FFs from one clock domain through ABC
 509      - Now always use BLIF as exchange format with ABC
 510      - Added support for "abc -script +<command_sequence>"
 511      - Improved standard ABC recipe
 512      - Added support for "keep" attribute to abc command
 513      - Added "abc -dff / -clk / -keepff" options
 514
 515  * Improvements to "eval" and "sat" framework:
 516      - Added support for "0" and "~0" in right-hand side -set expressions
 517      - Added "eval -set-undef" and "eval -table"
 518      - Added "sat -set-init" and "sat -set-init-*" for sequential problems
 519      - Added undef support to SAT solver, incl. various new "sat" options
 520      - Added correct support for === and !== for "eval" and "sat"
 521      - Added "sat -tempinduct" (default -seq is now non-induction sequential)
 522      - Added "sat -prove-asserts"
 523      - Complete rewrite of the 'freduce' command
 524      - Added "miter" command
 525      - Added "sat -show-inputs" and "sat -show-outputs"
 526      - Added "sat -ignore_unknown_cells" (now produce an error by default)
 527      - Added "sat -falsify"
 528      - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
 529      - Added "expose" command
 530      - Added support for @<sel_name> to sat and eval signal expressions
 531
 532  * Changes in the 'make test' framework and auxiliary test tools:
 533      - Added autotest.sh -p and -f options
 534      - Replaced autotest.sh ISIM support with XSIM support
 535      - Added test cases for SAT framework
 536
 537  * Added "abbreviated IDs":
 538      - Now $<something>$foo can be abbreviated as $foo.
 539      - Usually this last part is a unique id (from RTLIL::autoidx)
 540      - This abbreviated IDs are now also used in "show" output
 541
 542  * Other changes to selection framework:
 543      - Now */ is optional in */<mode>:<arg> expressions
 544      - Added "select -assert-none" and "select -assert-any"
 545      - Added support for matching modules by attribute (A:<expr>)
 546      - Added "select -none"
 547      - Added support for r:<expr> pattern for matching cell parameters
 548      - Added support for !=, <, <=, >=, > for attribute and parameter matching
 549      - Added support for %s for selecting sub-modules
 550      - Added support for %m for expanding selections to whole modules
 551      - Added support for i:*, o:* and x:* pattern for selecting module ports
 552      - Added support for s:<expr> pattern for matching wire width
 553      - Added support for %a operation to select wire aliases
 554
 555  * Various other changes to commands and options:
 556      - The "ls" command now supports wildcards
 557      - Added "show -pause" and "show -format dot"
 558      - Added "show -color" support for cells
 559      - Added "show -label" and "show -notitle"
 560      - Added "dump -m" and "dump -n"
 561      - Added "history" command
 562      - Added "rename -hide"
 563      - Added "connect" command
 564      - Added "splitnets -driver"
 565      - Added "opt_const -mux_undef"
 566      - Added "opt_const -mux_bool"
 567      - Added "opt_const -undriven"
 568      - Added "opt -mux_undef -mux_bool -undriven -purge"
 569      - Added "hierarchy -libdir"
 570      - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
 571      - Added "delete" command
 572      - Added "dump -append"
 573      - Added "setattr" and "setparam" commands
 574      - Added "design -stash/-copy-from/-copy-to"
 575      - Added "copy" command
 576      - Added "splice" command
 577