Merge pull request #1830 from boqwxp/qbfsat
[yosys.git] / CHANGELOG
1
2 List of major changes and improvements between releases
3 =======================================================
4
5
6 Yosys 0.9 .. Yosys 0.9-dev
7 --------------------------
8
9 * Various
10 - Added "write_xaiger" backend
11 - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
12 - Added "synth_xilinx -abc9" (experimental)
13 - Added "synth_ice40 -abc9" (experimental)
14 - Added "synth -abc9" (experimental)
15 - Added "script -scriptwire"
16 - Added "synth_xilinx -nocarry"
17 - Added "synth_xilinx -nowidelut"
18 - Added "synth_ecp5 -nowidelut"
19 - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
20 - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
21 - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
22 - Renamed labels in synth_intel (e.g. bram -> map_bram)
23 - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
24 - Added automatic gzip decompression for frontends
25 - Added $_NMUX_ cell type
26 - Added automatic gzip compression (based on filename extension) for backends
27 - Improve attribute and parameter encoding in JSON to avoid ambiguities between
28 bit vectors and strings containing [01xz]*
29 - Added "clkbufmap" pass
30 - Added "extractinv" pass and "invertible_pin" attribute
31 - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
32 - Added "synth_xilinx -ise" (experimental)
33 - Added "synth_xilinx -iopad"
34 - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
35 - Improvements in pmgen: subpattern and recursive matches
36 - Added "opt_share" pass, run as part of "opt -full"
37 - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
38 - Removed "ice40_unlut"
39 - Improvements in pmgen: slices, choices, define, generate
40 - Added "xilinx_srl" for Xilinx shift register extraction
41 - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
42 - Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
43 - Added "-match-init" option to "dff2dffs" pass
44 - Added "techmap_autopurge" support to techmap
45 - Added "add -mod <modname[s]>"
46 - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
47 - Added "ice40_dsp" for Lattice iCE40 DSP packing
48 - Added "xilinx_dsp" for Xilinx DSP packing
49 - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
50 - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
51 - "synth_ice40 -dsp" to infer DSP blocks
52 - Added latch support to synth_xilinx
53 - Added support for flip-flops with synchronous reset to synth_xilinx
54 - Added support for flip-flops with reset and enable to synth_xilinx
55 - Added "check -mapped"
56 - Added checking of SystemVerilog always block types (always_comb,
57 always_latch and always_ff)
58 - Added support for SystemVerilog wildcard port connections (.*)
59 - Added "xilinx_dffopt" pass
60 - Added "scratchpad" pass
61 - Added "abc9 -dff"
62 - Added "synth_xilinx -dff"
63 - Improved support of $readmem[hb] Memory Content File inclusion
64 - Added "opt_lut_ins" pass
65 - Added "logger" pass
66 - Removed "dffsr2dff" (use opt_rmdff instead)
67
68 Yosys 0.8 .. Yosys 0.9
69 ----------------------
70
71 * Various
72 - Many bugfixes and small improvements
73 - Added support for SystemVerilog interfaces and modports
74 - Added "write_edif -attrprop"
75 - Added "opt_lut" pass
76 - Added "gate2lut.v" techmap rule
77 - Added "rename -src"
78 - Added "equiv_opt" pass
79 - Added "flowmap" LUT mapping pass
80 - Added "rename -wire" to rename cells based on the wires they drive
81 - Added "bugpoint" for creating minimised testcases
82 - Added "write_edif -gndvccy"
83 - "write_verilog" to escape Verilog keywords
84 - Fixed sign handling of real constants
85 - "write_verilog" to write initial statement for initial flop state
86 - Added pmgen pattern matcher generator
87 - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
88 - Added "setundef -params" to replace undefined cell parameters
89 - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
90 - Fixed handling of defparam when default_nettype is none
91 - Fixed "wreduce" flipflop handling
92 - Fixed FIRRTL to Verilog process instance subfield assignment
93 - Added "write_verilog -siminit"
94 - Several fixes and improvements for mem2reg memories
95 - Fixed handling of task output ports in clocked always blocks
96 - Improved handling of and-with-1 and or-with-0 in "opt_expr"
97 - Added "read_aiger" frontend
98 - Added "mutate" pass
99 - Added "hdlname" attribute
100 - Added "rename -output"
101 - Added "read_ilang -lib"
102 - Improved "proc" full_case detection and handling
103 - Added "whitebox" and "lib_whitebox" attributes
104 - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
105 - Added Python bindings and support for Python plug-ins
106 - Added "pmux2shiftx"
107 - Added log_debug framework for reduced default verbosity
108 - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
109 - Added "peepopt" peephole optimisation pass using pmgen
110 - Added approximate support for SystemVerilog "var" keyword
111 - Added parsing of "specify" blocks into $specrule and $specify[23]
112 - Added support for attributes on parameters and localparams
113 - Added support for parsing attributes on port connections
114 - Added "wreduce -keepdc"
115 - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
116 - Added Verilog wand/wor wire type support
117 - Added support for elaboration system tasks
118 - Added "muxcover -mux{4,8,16}=<cost>"
119 - Added "muxcover -dmux=<cost>"
120 - Added "muxcover -nopartial"
121 - Added "muxpack" pass
122 - Added "pmux2shiftx -norange"
123 - Added support for "~" in filename parsing
124 - Added "read_verilog -pwires" feature to turn parameters into wires
125 - Fixed sign extension of unsized constants with 'bx and 'bz MSB
126 - Fixed genvar to be a signed type
127 - Added support for attributes on case rules
128 - Added "upto" and "offset" to JSON frontend and backend
129 - Several liberty file parser improvements
130 - Fixed handling of more complex BRAM patterns
131 - Add "write_aiger -I -O -B"
132
133 * Formal Verification
134 - Added $changed support to read_verilog
135 - Added "read_verilog -noassert -noassume -assert-assumes"
136 - Added btor ops for $mul, $div, $mod and $concat
137 - Added yosys-smtbmc support for btor witnesses
138 - Added "supercover" pass
139 - Fixed $global_clock handling vs autowire
140 - Added $dffsr support to "async2sync"
141 - Added "fmcombine" pass
142 - Added memory init support in "write_btor"
143 - Added "cutpoint" pass
144 - Changed "ne" to "neq" in btor2 output
145 - Added support for SVA "final" keyword
146 - Added "fmcombine -initeq -anyeq"
147 - Added timescale and generated-by header to yosys-smtbmc vcd output
148 - Improved BTOR2 handling of undriven wires
149
150 * Verific support
151 - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
152 - Improved support for asymmetric memories
153 - Added "verific -chparam"
154 - Fixed "verific -extnets" for more complex situations
155 - Added "read -verific" and "read -noverific"
156 - Added "hierarchy -chparam"
157
158 * New back-ends
159 - Added initial Anlogic support
160 - Added initial SmartFusion2 and IGLOO2 support
161
162 * ECP5 support
163 - Added "synth_ecp5 -nowidelut"
164 - Added BRAM inference support to "synth_ecp5"
165 - Added support for transforming Diamond IO and flipflop primitives
166
167 * iCE40 support
168 - Added "ice40_unlut" pass
169 - Added "synth_ice40 -relut"
170 - Added "synth_ice40 -noabc"
171 - Added "synth_ice40 -dffe_min_ce_use"
172 - Added DSP inference support using pmgen
173 - Added support for initialising BRAM primitives from a file
174 - Added iCE40 Ultra RGB LED driver cells
175
176 * Xilinx support
177 - Use "write_edif -pvector bra" for Xilinx EDIF files
178 - Fixes for VPR place and route support with "synth_xilinx"
179 - Added more cell simulation models
180 - Added "synth_xilinx -family"
181 - Added "stat -tech xilinx" to estimate logic cell usage
182 - Added "synth_xilinx -nocarry"
183 - Added "synth_xilinx -nowidelut"
184 - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
185 - Added support for mapping RAM32X1D
186
187 Yosys 0.7 .. Yosys 0.8
188 ----------------------
189
190 * Various
191 - Many bugfixes and small improvements
192 - Strip debug symbols from installed binary
193 - Replace -ignore_redef with -[no]overwrite in front-ends
194 - Added write_verilog hex dump support, add -nohex option
195 - Added "write_verilog -decimal"
196 - Added "scc -set_attr"
197 - Added "verilog_defines" command
198 - Remember defines from one read_verilog to next
199 - Added support for hierarchical defparam
200 - Added FIRRTL back-end
201 - Improved ABC default scripts
202 - Added "design -reset-vlog"
203 - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
204 - Added Verilog $rtoi and $itor support
205 - Added "check -initdrv"
206 - Added "read_blif -wideports"
207 - Added support for SystemVerilog "++" and "--" operators
208 - Added support for SystemVerilog unique, unique0, and priority case
209 - Added "write_edif" options for edif "flavors"
210 - Added support for resetall compiler directive
211 - Added simple C beck-end (bitwise combinatorical only atm)
212 - Added $_ANDNOT_ and $_ORNOT_ cell types
213 - Added cell library aliases to "abc -g"
214 - Added "setundef -anyseq"
215 - Added "chtype" command
216 - Added "design -import"
217 - Added "write_table" command
218 - Added "read_json" command
219 - Added "sim" command
220 - Added "extract_fa" and "extract_reduce" commands
221 - Added "extract_counter" command
222 - Added "opt_demorgan" command
223 - Added support for $size and $bits SystemVerilog functions
224 - Added "blackbox" command
225 - Added "ltp" command
226 - Added support for editline as replacement for readline
227 - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
228 - Added "yosys -E" for creating Makefile dependencies files
229 - Added "synth -noshare"
230 - Added "memory_nordff"
231 - Added "setundef -undef -expose -anyconst"
232 - Added "expose -input"
233 - Added specify/specparam parser support (simply ignore them)
234 - Added "write_blif -inames -iattr"
235 - Added "hierarchy -simcheck"
236 - Added an option to statically link abc into yosys
237 - Added protobuf back-end
238 - Added BLIF parsing support for .conn and .cname
239 - Added read_verilog error checking for reg/wire/logic misuse
240 - Added "make coverage" and ENABLE_GCOV build option
241
242 * Changes in Yosys APIs
243 - Added ConstEval defaultval feature
244 - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
245 - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
246 - Added log_file_warning() and log_file_error() functions
247
248 * Formal Verification
249 - Added "write_aiger"
250 - Added "yosys-smtbmc --aig"
251 - Added "always <positive_int>" to .smtc format
252 - Added $cover cell type and support for cover properties
253 - Added $fair/$live cell type and support for liveness properties
254 - Added smtbmc support for memory vcd dumping
255 - Added "chformal" command
256 - Added "write_smt2 -stbv" and "write_smt2 -stdt"
257 - Fix equiv_simple, old behavior now available with "equiv_simple -short"
258 - Change to Yices2 as default SMT solver (it is GPL now)
259 - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
260 - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
261 - Added a brand new "write_btor" command for BTOR2
262 - Added clk2fflogic memory support and other improvements
263 - Added "async memory write" support to write_smt2
264 - Simulate clock toggling in yosys-smtbmc VCD output
265 - Added $allseq/$allconst cells for EA-solving
266 - Make -nordff the default in "prep"
267 - Added (* gclk *) attribute
268 - Added "async2sync" pass for single-clock designs with async resets
269
270 * Verific support
271 - Many improvements in Verific front-end
272 - Added proper handling of concurent SVA properties
273 - Map "const" and "rand const" to $anyseq/$anyconst
274 - Added "verific -import -flatten" and "verific -import -extnets"
275 - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
276 - Remove PSL support (because PSL has been removed in upstream Verific)
277 - Improve integration with "hierarchy" command design elaboration
278 - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
279 - Added simpilied "read" command that automatically uses verific if available
280 - Added "verific -set-<severity> <msg_id>.."
281 - Added "verific -work <libname>"
282
283 * New back-ends
284 - Added initial Coolrunner-II support
285 - Added initial eASIC support
286 - Added initial ECP5 support
287
288 * GreenPAK Support
289 - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
290
291 * iCE40 Support
292 - Add "synth_ice40 -vpr"
293 - Add "synth_ice40 -nodffe"
294 - Add "synth_ice40 -json"
295 - Add Support for UltraPlus cells
296
297 * MAX10 and Cyclone IV Support
298 - Added initial version of metacommand "synth_intel".
299 - Improved write_verilog command to produce VQM netlist for Quartus Prime.
300 - Added support for MAX10 FPGA family synthesis.
301 - Added support for Cyclone IV family synthesis.
302 - Added example of implementation for DE2i-150 board.
303 - Added example of implementation for MAX10 development kit.
304 - Added LFSR example from Asic World.
305 - Added "dffinit -highlow" for mapping to Intel primitives
306
307
308 Yosys 0.6 .. Yosys 0.7
309 ----------------------
310
311 * Various
312 - Added "yosys -D" feature
313 - Added support for installed plugins in $(DATDIR)/plugins/
314 - Renamed opt_const to opt_expr
315 - Renamed opt_share to opt_merge
316 - Added "prep -flatten" and "synth -flatten"
317 - Added "prep -auto-top" and "synth -auto-top"
318 - Using "mfs" and "lutpack" in ABC lut mapping
319 - Support for abstract modules in chparam
320 - Cleanup abstract modules at end of "hierarchy -top"
321 - Added tristate buffer support to iopadmap
322 - Added opt_expr support for div/mod by power-of-two
323 - Added "select -assert-min <N> -assert-max <N>"
324 - Added "attrmvcp" pass
325 - Added "attrmap" command
326 - Added "tee +INT -INT"
327 - Added "zinit" pass
328 - Added "setparam -type"
329 - Added "shregmap" pass
330 - Added "setundef -init"
331 - Added "nlutmap -assert"
332 - Added $sop cell type and "abc -sop -I <num> -P <num>"
333 - Added "dc2" to default ABC scripts
334 - Added "deminout"
335 - Added "insbuf" command
336 - Added "prep -nomem"
337 - Added "opt_rmdff -keepdc"
338 - Added "prep -nokeepdc"
339 - Added initial version of "synth_gowin"
340 - Added "fsm_expand -full"
341 - Added support for fsm_encoding="user"
342 - Many improvements in GreenPAK4 support
343 - Added black box modules for all Xilinx 7-series lib cells
344 - Added synth_ice40 support for latches via logic loops
345 - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
346
347 * Build System
348 - Added ABCEXTERNAL and ABCURL make variables
349 - Added BINDIR, LIBDIR, and DATDIR make variables
350 - Added PKG_CONFIG make variable
351 - Added SEED make variable (for "make test")
352 - Added YOSYS_VER_STR make variable
353 - Updated min GCC requirement to GCC 4.8
354 - Updated required Bison version to Bison 3.x
355
356 * Internal APIs
357 - Added ast.h to exported headers
358 - Added ScriptPass helper class for script-like passes
359 - Added CellEdgesDatabase API
360
361 * Front-ends and Back-ends
362 - Added filename glob support to all front-ends
363 - Added avail (black-box) module params to ilang format
364 - Added $display %m support
365 - Added support for $stop Verilog system task
366 - Added support for SystemVerilog packages
367 - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
368 - Added support for "active high" and "active low" latches in read_blif and write_blif
369 - Use init value "2" for all uninitialized FFs in BLIF back-end
370 - Added "read_blif -sop"
371 - Added "write_blif -noalias"
372 - Added various write_blif options for VTR support
373 - write_json: also write module attributes.
374 - Added "write_verilog -nodec -nostr -defparam"
375 - Added "read_verilog -norestrict -assume-asserts"
376 - Added support for bus interfaces to "read_liberty -lib"
377 - Added liberty parser support for types within cell decls
378 - Added "write_verilog -renameprefix -v"
379 - Added "write_edif -nogndvcc"
380
381 * Formal Verification
382 - Support for hierarchical designs in smt2 back-end
383 - Yosys-smtbmc: Support for hierarchical VCD dumping
384 - Added $initstate cell type and vlog function
385 - Added $anyconst and $anyseq cell types and vlog functions
386 - Added printing of code loc of failed asserts to yosys-smtbmc
387 - Added memory_memx pass, "memory -memx", and "prep -memx"
388 - Added "proc_mux -ifx"
389 - Added "yosys-smtbmc -g"
390 - Deprecated "write_smt2 -regs" (by default on now)
391 - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
392 - Added support for memories to smtio.py
393 - Added "yosys-smtbmc --dump-vlogtb"
394 - Added "yosys-smtbmc --smtc --dump-smtc"
395 - Added "yosys-smtbmc --dump-all"
396 - Added assertpmux command
397 - Added "yosys-smtbmc --unroll"
398 - Added $past, $stable, $rose, $fell SVA functions
399 - Added "yosys-smtbmc --noinfo and --dummy"
400 - Added "yosys-smtbmc --noincr"
401 - Added "yosys-smtbmc --cex <filename>"
402 - Added $ff and $_FF_ cell types
403 - Added $global_clock verilog syntax support for creating $ff cells
404 - Added clk2fflogic
405
406
407 Yosys 0.5 .. Yosys 0.6
408 ----------------------
409
410 * Various
411 - Added Contributor Covenant Code of Conduct
412 - Various improvements in dict<> and pool<>
413 - Added hashlib::mfp and refactored SigMap
414 - Improved support for reals as module parameters
415 - Various improvements in SMT2 back-end
416 - Added "keep_hierarchy" attribute
417 - Verilog front-end: define `BLACKBOX in -lib mode
418 - Added API for converting internal cells to AIGs
419 - Added ENABLE_LIBYOSYS Makefile option
420 - Removed "techmap -share_map" (use "-map +/filename" instead)
421 - Switched all Python scripts to Python 3
422 - Added support for $display()/$write() and $finish() to Verilog front-end
423 - Added "yosys-smtbmc" formal verification flow
424 - Added options for clang sanitizers to Makefile
425
426 * New commands and options
427 - Added "scc -expect <N> -nofeedback"
428 - Added "proc_dlatch"
429 - Added "check"
430 - Added "select %xe %cie %coe %M %C %R"
431 - Added "sat -dump_json" (WaveJSON format)
432 - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
433 - Added "sat -stepsize" and "sat -tempinduct-step"
434 - Added "sat -show-regs -show-public -show-all"
435 - Added "write_json" (Native Yosys JSON format)
436 - Added "write_blif -attr"
437 - Added "dffinit"
438 - Added "chparam"
439 - Added "muxcover"
440 - Added "pmuxtree"
441 - Added memory_bram "make_outreg" feature
442 - Added "splice -wires"
443 - Added "dff2dffe -direct-match"
444 - Added simplemap $lut support
445 - Added "read_blif"
446 - Added "opt_share -share_all"
447 - Added "aigmap"
448 - Added "write_smt2 -mem -regs -wires"
449 - Added "memory -nordff"
450 - Added "write_smv"
451 - Added "synth -nordff -noalumacc"
452 - Added "rename -top new_name"
453 - Added "opt_const -clkinv"
454 - Added "synth -nofsm"
455 - Added "miter -assert"
456 - Added "read_verilog -noautowire"
457 - Added "read_verilog -nodpi"
458 - Added "tribuf"
459 - Added "lut2mux"
460 - Added "nlutmap"
461 - Added "qwp"
462 - Added "test_cell -noeval"
463 - Added "edgetypes"
464 - Added "equiv_struct"
465 - Added "equiv_purge"
466 - Added "equiv_mark"
467 - Added "equiv_add -try -cell"
468 - Added "singleton"
469 - Added "abc -g -luts"
470 - Added "torder"
471 - Added "write_blif -cname"
472 - Added "submod -copy"
473 - Added "dffsr2dff"
474 - Added "stat -liberty"
475
476 * Synthesis metacommands
477 - Various improvements in synth_xilinx
478 - Added synth_ice40 and synth_greenpak4
479 - Added "prep" metacommand for "synthesis lite"
480
481 * Cell library changes
482 - Added cell types to "help" system
483 - Added $meminit cell type
484 - Added $assume cell type
485 - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
486 - Added $tribuf and $_TBUF_ cell types
487 - Added read-enable to memory model
488
489 * YosysJS
490 - Various improvements in emscripten build
491 - Added alternative webworker-based JS API
492 - Added a few example applications
493
494
495 Yosys 0.4 .. Yosys 0.5
496 ----------------------
497
498 * API changes
499 - Added log_warning()
500 - Added eval_select_args() and eval_select_op()
501 - Added cell->known(), cell->input(portname), cell->output(portname)
502 - Skip blackbox modules in design->selected_modules()
503 - Replaced std::map<> and std::set<> with dict<> and pool<>
504 - New SigSpec::extend() is what used to be SigSpec::extend_u0()
505 - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
506
507 * Cell library changes
508 - Added flip-flops with enable ($dffe etc.)
509 - Added $equiv cells for equivalence checking framework
510
511 * Various
512 - Updated ABC to hg rev 61ad5f908c03
513 - Added clock domain partitioning to ABC pass
514 - Improved plugin building (see "yosys-config --build")
515 - Added ENABLE_NDEBUG Makefile flag for high-performance builds
516 - Added "yosys -d", "yosys -L" and other driver improvements
517 - Added support for multi-bit (array) cell ports to "write_edif"
518 - Now printing most output to stdout, not stderr
519 - Added "onehot" attribute (set by "fsm_map")
520 - Various performance improvements
521 - Vastly improved Xilinx flow
522 - Added "make unsintall"
523
524 * Equivalence checking
525 - Added equivalence checking commands:
526 equiv_make equiv_simple equiv_status
527 equiv_induct equiv_miter
528 equiv_add equiv_remove
529
530 * Block RAM support:
531 - Added "memory_bram" command
532 - Added BRAM support to Xilinx flow
533
534 * Other New Commands and Options
535 - Added "dff2dffe"
536 - Added "fsm -encfile"
537 - Added "dfflibmap -prepare"
538 - Added "write_blid -unbuf -undef -blackbox"
539 - Added "write_smt2" for writing SMT-LIBv2 files
540 - Added "test_cell -w -muxdiv"
541 - Added "select -read"
542
543
544 Yosys 0.3.0 .. Yosys 0.4
545 ------------------------
546
547 * Platform Support
548 - Added support for mxe-based cross-builds for win32
549 - Added sourcecode-export as VisualStudio project
550 - Added experimental EMCC (JavaScript) support
551
552 * Verilog Frontend
553 - Added -sv option for SystemVerilog (and automatic *.sv file support)
554 - Added support for real-valued constants and constant expressions
555 - Added support for non-standard "via_celltype" attribute on task/func
556 - Added support for non-standard "module mod_name(...);" syntax
557 - Added support for non-standard """ macro bodies
558 - Added support for array with more than one dimension
559 - Added support for $readmemh and $readmemb
560 - Added support for DPI functions
561
562 * Changes in internal cell library
563 - Added $shift and $shiftx cell types
564 - Added $alu, $lcu, $fa and $macc cell types
565 - Removed $bu0 and $safe_pmux cell types
566 - $mem/$memwr WR_EN input is now a per-data-bit enable signal
567 - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
568 - Renamed ports of $lut cells (from I->O to A->Y)
569 - Renamed $_INV_ to $_NOT_
570
571 * Changes for simple synthesis flows
572 - There is now a "synth" command with a recommended default script
573 - Many improvements in synthesis of arithmetic functions to gates
574 - Multipliers and adders with many operands are using carry-save adder trees
575 - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
576 - Various new high-level optimizations on RTL netlist
577 - Various improvements in FSM optimization
578 - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
579
580 * Changes in internal APIs and RTLIL
581 - Added log_id() and log_cell() helper functions
582 - Added function-like cell creation helpers
583 - Added GetSize() function (like .size() but with int)
584 - Major refactoring of RTLIL::Module and related classes
585 - Major refactoring of RTLIL::SigSpec and related classes
586 - Now RTLIL::IdString is essentially an int
587 - Added macros for code coverage counters
588 - Added some Makefile magic for pretty make logs
589 - Added "kernel/yosys.h" with all the core definitions
590 - Changed a lot of code from FILE* to c++ streams
591 - Added RTLIL::Monitor API and "trace" command
592 - Added "Yosys" C++ namespace
593
594 * Changes relevant to SAT solving
595 - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
596 - Added native ezSAT support for vector shift ops
597 - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
598
599 * New commands (or large improvements to commands)
600 - Added "synth" command with default script
601 - Added "share" (finally some real resource sharing)
602 - Added "memory_share" (reduce number of ports on memories)
603 - Added "wreduce" and "alumacc" commands
604 - Added "opt -keepdc -fine -full -fast"
605 - Added some "test_*" commands
606
607 * Various other changes
608 - Added %D and %c select operators
609 - Added support for labels in yosys scripts
610 - Added support for here-documents in yosys scripts
611 - Support "+/" prefix for files from proc_share_dir
612 - Added "autoidx" statement to ilang language
613 - Switched from "yosys-svgviewer" to "xdot"
614 - Renamed "stdcells.v" to "techmap.v"
615 - Various bug fixes and small improvements
616 - Improved welcome and bye messages
617
618
619 Yosys 0.2.0 .. Yosys 0.3.0
620 --------------------------
621
622 * Driver program and overall behavior:
623 - Added "design -push" and "design -pop"
624 - Added "tee" command for redirecting log output
625
626 * Changes in the internal cell library:
627 - Added $dlatchsr and $_DLATCHSR_???_ cell types
628
629 * Improvements in Verilog frontend:
630 - Improved support for const functions (case, always, repeat)
631 - The generate..endgenerate keywords are now optional
632 - Added support for arrays of module instances
633 - Added support for "`default_nettype" directive
634 - Added support for "`line" directive
635
636 * Other front- and back-ends:
637 - Various changes to "write_blif" options
638 - Various improvements in EDIF backend
639 - Added "vhdl2verilog" pseudo-front-end
640 - Added "verific" pseudo-front-end
641
642 * Improvements in technology mapping:
643 - Added support for recursive techmap
644 - Added CONSTMSK and CONSTVAL features to techmap
645 - Added _TECHMAP_CONNMAP_*_ feature to techmap
646 - Added _TECHMAP_REPLACE_ feature to techmap
647 - Added "connwrappers" command for wrap-extract-unwrap method
648 - Added "extract -map %<design_name>" feature
649 - Added "extract -ignore_param ..." and "extract -ignore_parameters"
650 - Added "techmap -max_iter" option
651
652 * Improvements to "eval" and "sat" framework:
653 - Now include a copy of Minisat (with build fixes applied)
654 - Switched to Minisat::SimpSolver as SAT back-end
655 - Added "sat -dump_vcd" feature
656 - Added "sat -dump_cnf" feature
657 - Added "sat -initsteps <N>" feature
658 - Added "freduce -stop <N>" feature
659 - Added "freduce -dump <prefix>" feature
660
661 * Integration with ABC:
662 - Updated ABC rev to 7600ffb9340c
663
664 * Improvements in the internal APIs:
665 - Added RTLIL::Module::add... helper methods
666 - Various build fixes for OSX (Darwin) and OpenBSD
667
668
669 Yosys 0.1.0 .. Yosys 0.2.0
670 --------------------------
671
672 * Changes to the driver program:
673 - Added "yosys -h" and "yosys -H"
674 - Added support for backslash line continuation in scripts
675 - Added support for #-comments in same line as command
676 - Added "echo" and "log" commands
677
678 * Improvements in Verilog frontend:
679 - Added support for local registers in named blocks
680 - Added support for "case" in "generate" blocks
681 - Added support for $clog2 system function
682 - Added support for basic SystemVerilog assert statements
683 - Added preprocessor support for macro arguments
684 - Added preprocessor support for `elsif statement
685 - Added "verilog_defaults" command
686 - Added read_verilog -icells option
687 - Added support for constant sizes from parameters
688 - Added "read_verilog -setattr"
689 - Added support for function returning 'integer'
690 - Added limited support for function calls in parameter values
691 - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
692
693 * Other front- and back-ends:
694 - Added BTOR backend
695 - Added Liberty frontend
696
697 * Improvements in technology mapping:
698 - The "dfflibmap" command now strongly prefers solutions with
699 no inverters in clock paths
700 - The "dfflibmap" command now prefers cells with smaller area
701 - Added support for multiple -map options to techmap
702 - Added "dfflibmap" support for //-comments in liberty files
703 - Added "memory_unpack" command to revert "memory_collect"
704 - Added standard techmap rule "techmap -share_map pmux2mux.v"
705 - Added "iopadmap -bits"
706 - Added "setundef" command
707 - Added "hilomap" command
708
709 * Changes in the internal cell library:
710 - Major rewrite of simlib.v for better compatibility with other tools
711 - Added PRIORITY parameter to $memwr cells
712 - Added TRANSPARENT parameter to $memrd cells
713 - Added RD_TRANSPARENT parameter to $mem cells
714 - Added $bu0 cell (always 0-extend, even undef MSB)
715 - Added $assert cell type
716 - Added $slice and $concat cell types
717
718 * Integration with ABC:
719 - Updated ABC to hg rev 2058c8ccea68
720 - Tighter integration of ABC build with Yosys build. The make
721 targets 'make abc' and 'make install-abc' are now obsolete.
722 - Added support for passing FFs from one clock domain through ABC
723 - Now always use BLIF as exchange format with ABC
724 - Added support for "abc -script +<command_sequence>"
725 - Improved standard ABC recipe
726 - Added support for "keep" attribute to abc command
727 - Added "abc -dff / -clk / -keepff" options
728
729 * Improvements to "eval" and "sat" framework:
730 - Added support for "0" and "~0" in right-hand side -set expressions
731 - Added "eval -set-undef" and "eval -table"
732 - Added "sat -set-init" and "sat -set-init-*" for sequential problems
733 - Added undef support to SAT solver, incl. various new "sat" options
734 - Added correct support for === and !== for "eval" and "sat"
735 - Added "sat -tempinduct" (default -seq is now non-induction sequential)
736 - Added "sat -prove-asserts"
737 - Complete rewrite of the 'freduce' command
738 - Added "miter" command
739 - Added "sat -show-inputs" and "sat -show-outputs"
740 - Added "sat -ignore_unknown_cells" (now produce an error by default)
741 - Added "sat -falsify"
742 - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
743 - Added "expose" command
744 - Added support for @<sel_name> to sat and eval signal expressions
745
746 * Changes in the 'make test' framework and auxiliary test tools:
747 - Added autotest.sh -p and -f options
748 - Replaced autotest.sh ISIM support with XSIM support
749 - Added test cases for SAT framework
750
751 * Added "abbreviated IDs":
752 - Now $<something>$foo can be abbreviated as $foo.
753 - Usually this last part is a unique id (from RTLIL::autoidx)
754 - This abbreviated IDs are now also used in "show" output
755
756 * Other changes to selection framework:
757 - Now */ is optional in */<mode>:<arg> expressions
758 - Added "select -assert-none" and "select -assert-any"
759 - Added support for matching modules by attribute (A:<expr>)
760 - Added "select -none"
761 - Added support for r:<expr> pattern for matching cell parameters
762 - Added support for !=, <, <=, >=, > for attribute and parameter matching
763 - Added support for %s for selecting sub-modules
764 - Added support for %m for expanding selections to whole modules
765 - Added support for i:*, o:* and x:* pattern for selecting module ports
766 - Added support for s:<expr> pattern for matching wire width
767 - Added support for %a operation to select wire aliases
768
769 * Various other changes to commands and options:
770 - The "ls" command now supports wildcards
771 - Added "show -pause" and "show -format dot"
772 - Added "show -color" support for cells
773 - Added "show -label" and "show -notitle"
774 - Added "dump -m" and "dump -n"
775 - Added "history" command
776 - Added "rename -hide"
777 - Added "connect" command
778 - Added "splitnets -driver"
779 - Added "opt_const -mux_undef"
780 - Added "opt_const -mux_bool"
781 - Added "opt_const -undriven"
782 - Added "opt -mux_undef -mux_bool -undriven -purge"
783 - Added "hierarchy -libdir"
784 - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
785 - Added "delete" command
786 - Added "dump -append"
787 - Added "setattr" and "setparam" commands
788 - Added "design -stash/-copy-from/-copy-to"
789 - Added "copy" command
790 - Added "splice" command
791