CHANGELOG

   1
   2 List of major changes and improvements between releases
   3 =======================================================
   4
   5
   6 Yosys 0.7 .. Yosys ???
   7 ----------------------
   8
   9  * MAX10 and Cyclone IV Support
  10     - Added initial version of metacommand "synth_intel".
  11     - Improved write_verilog command to produce VQM netlist for Quartus Prime.
  12     - Added support for MAX10 FPGA family synthesis.
  13     - Added support for Cyclone IV family synthesis.
  14     - Added example of implementation for DE2i-150 board.
  15     - Added example of implementation for MAX10 development kit.
  16     - Added LFSR example from Asic World.
  17
  18
  19 Yosys 0.6 .. Yosys 0.7
  20 ----------------------
  21
  22  * Various
  23     - Added "yosys -D" feature
  24     - Added support for installed plugins in $(DATDIR)/plugins/
  25     - Renamed opt_const to opt_expr
  26     - Renamed opt_share to opt_merge
  27     - Added "prep -flatten" and "synth -flatten"
  28     - Added "prep -auto-top" and "synth -auto-top"
  29     - Using "mfs" and "lutpack" in ABC lut mapping
  30     - Support for abstract modules in chparam
  31     - Cleanup abstract modules at end of "hierarchy -top"
  32     - Added tristate buffer support to iopadmap
  33     - Added opt_expr support for div/mod by power-of-two
  34     - Added "select -assert-min <N> -assert-max <N>"
  35     - Added "attrmvcp" pass
  36     - Added "attrmap" command
  37     - Added "tee +INT -INT"
  38     - Added "zinit" pass
  39     - Added "setparam -type"
  40     - Added "shregmap" pass
  41     - Added "setundef -init"
  42     - Added "nlutmap -assert"
  43     - Added $sop cell type and "abc -sop -I <num> -P <num>"
  44     - Added "dc2" to default ABC scripts
  45     - Added "deminout"
  46     - Added "insbuf" command
  47     - Added "prep -nomem"
  48     - Added "opt_rmdff -keepdc"
  49     - Added "prep -nokeepdc"
  50     - Added initial version of "synth_gowin"
  51     - Added "fsm_expand -full"
  52     - Added support for fsm_encoding="user"
  53     - Many improvements in GreenPAK4 support
  54     - Added black box modules for all Xilinx 7-series lib cells
  55     - Added synth_ice40 support for latches via logic loops
  56     - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
  57
  58  * Build System
  59     - Added ABCEXTERNAL and ABCURL make variables
  60     - Added BINDIR, LIBDIR, and DATDIR make variables
  61     - Added PKG_CONFIG make variable
  62     - Added SEED make variable (for "make test")
  63     - Added YOSYS_VER_STR make variable
  64     - Updated min GCC requirement to GCC 4.8
  65     - Updated required Bison version to Bison 3.x
  66
  67  * Internal APIs
  68     - Added ast.h to exported headers
  69     - Added ScriptPass helper class for script-like passes
  70     - Added CellEdgesDatabase API
  71
  72  * Front-ends and Back-ends
  73     - Added filename glob support to all front-ends
  74     - Added avail (black-box) module params to ilang format
  75     - Added $display %m support
  76     - Added support for $stop Verilog system task
  77     - Added support for SystemVerilog packages
  78     - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
  79     - Added support for "active high" and "active low" latches in read_blif and write_blif
  80     - Use init value "2" for all uninitialized FFs in BLIF back-end
  81     - Added "read_blif -sop"
  82     - Added "write_blif -noalias"
  83     - Added various write_blif options for VTR support
  84     - write_json: also write module attributes.
  85     - Added "write_verilog -nodec -nostr -defparam"
  86     - Added "read_verilog -norestrict -assume-asserts"
  87     - Added support for bus interfaces to "read_liberty -lib"
  88     - Added liberty parser support for types within cell decls
  89     - Added "write_verilog -renameprefix -v"
  90     - Added "write_edif -nogndvcc"
  91
  92  * Formal Verification
  93     - Support for hierarchical designs in smt2 back-end
  94     - Yosys-smtbmc: Support for hierarchical VCD dumping
  95     - Added $initstate cell type and vlog function
  96     - Added $anyconst and $anyseq cell types and vlog functions
  97     - Added printing of code loc of failed asserts to yosys-smtbmc
  98     - Added memory_memx pass, "memory -memx", and "prep -memx"
  99     - Added "proc_mux -ifx"
 100     - Added "yosys-smtbmc -g"
 101     - Deprecated "write_smt2 -regs" (by default on now)
 102     - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
 103     - Added support for memories to smtio.py
 104     - Added "yosys-smtbmc --dump-vlogtb"
 105     - Added "yosys-smtbmc --smtc --dump-smtc"
 106     - Added "yosys-smtbmc --dump-all"
 107     - Added assertpmux command
 108     - Added "yosys-smtbmc --unroll"
 109     - Added $past, $stable, $rose, $fell SVA functions
 110     - Added "yosys-smtbmc --noinfo and --dummy"
 111     - Added "yosys-smtbmc --noincr"
 112     - Added "yosys-smtbmc --cex <filename>"
 113     - Added $ff and $_FF_ cell types
 114     - Added $global_clock verilog syntax support for creating $ff cells
 115     - Added clk2fflogic
 116
 117
 118 Yosys 0.5 .. Yosys 0.6
 119 ----------------------
 120
 121  * Various
 122      - Added Contributor Covenant Code of Conduct
 123      - Various improvements in dict<> and pool<>
 124      - Added hashlib::mfp and refactored SigMap
 125      - Improved support for reals as module parameters
 126      - Various improvements in SMT2 back-end
 127      - Added "keep_hierarchy" attribute
 128      - Verilog front-end: define `BLACKBOX in -lib mode
 129      - Added API for converting internal cells to AIGs
 130      - Added ENABLE_LIBYOSYS Makefile option
 131      - Removed "techmap -share_map" (use "-map +/filename" instead)
 132      - Switched all Python scripts to Python 3
 133      - Added support for $display()/$write() and $finish() to Verilog front-end
 134      - Added "yosys-smtbmc" formal verification flow
 135      - Added options for clang sanitizers to Makefile
 136
 137  * New commands and options
 138      - Added "scc -expect <N> -nofeedback"
 139      - Added "proc_dlatch"
 140      - Added "check"
 141      - Added "select %xe %cie %coe %M %C %R"
 142      - Added "sat -dump_json" (WaveJSON format)
 143      - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
 144      - Added "sat -stepsize" and "sat -tempinduct-step"
 145      - Added "sat -show-regs -show-public -show-all"
 146      - Added "write_json" (Native Yosys JSON format)
 147      - Added "write_blif -attr"
 148      - Added "dffinit"
 149      - Added "chparam"
 150      - Added "muxcover"
 151      - Added "pmuxtree"
 152      - Added memory_bram "make_outreg" feature
 153      - Added "splice -wires"
 154      - Added "dff2dffe -direct-match"
 155      - Added simplemap $lut support
 156      - Added "read_blif"
 157      - Added "opt_share -share_all"
 158      - Added "aigmap"
 159      - Added "write_smt2 -mem -regs -wires"
 160      - Added "memory -nordff"
 161      - Added "write_smv"
 162      - Added "synth -nordff -noalumacc"
 163      - Added "rename -top new_name"
 164      - Added "opt_const -clkinv"
 165      - Added "synth -nofsm"
 166      - Added "miter -assert"
 167      - Added "read_verilog -noautowire"
 168      - Added "read_verilog -nodpi"
 169      - Added "tribuf"
 170      - Added "lut2mux"
 171      - Added "nlutmap"
 172      - Added "qwp"
 173      - Added "test_cell -noeval"
 174      - Added "edgetypes"
 175      - Added "equiv_struct"
 176      - Added "equiv_purge"
 177      - Added "equiv_mark"
 178      - Added "equiv_add -try -cell"
 179      - Added "singleton"
 180      - Added "abc -g -luts"
 181      - Added "torder"
 182      - Added "write_blif -cname"
 183      - Added "submod -copy"
 184      - Added "dffsr2dff"
 185      - Added "stat -liberty"
 186
 187  * Synthesis metacommands
 188      - Various improvements in synth_xilinx
 189      - Added synth_ice40 and synth_greenpak4
 190      - Added "prep" metacommand for "synthesis lite"
 191
 192  * Cell library changes
 193      - Added cell types to "help" system
 194      - Added $meminit cell type
 195      - Added $assume cell type
 196      - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
 197      - Added $tribuf and $_TBUF_ cell types
 198      - Added read-enable to memory model
 199
 200  * YosysJS
 201      - Various improvements in emscripten build
 202      - Added alternative webworker-based JS API
 203      - Added a few example applications
 204
 205
 206 Yosys 0.4 .. Yosys 0.5
 207 ----------------------
 208
 209  * API changes
 210      - Added log_warning()
 211      - Added eval_select_args() and eval_select_op()
 212      - Added cell->known(), cell->input(portname), cell->output(portname)
 213      - Skip blackbox modules in design->selected_modules()
 214      - Replaced std::map<> and std::set<> with dict<> and pool<>
 215      - New SigSpec::extend() is what used to be SigSpec::extend_u0()
 216      - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
 217
 218  * Cell library changes
 219      - Added flip-flops with enable ($dffe etc.)
 220      - Added $equiv cells for equivalence checking framework
 221
 222  * Various
 223      - Updated ABC to hg rev 61ad5f908c03
 224      - Added clock domain partitioning to ABC pass
 225      - Improved plugin building (see "yosys-config --build")
 226      - Added ENABLE_NDEBUG Makefile flag for high-performance builds
 227      - Added "yosys -d", "yosys -L" and other driver improvements
 228      - Added support for multi-bit (array) cell ports to "write_edif"
 229      - Now printing most output to stdout, not stderr
 230      - Added "onehot" attribute (set by "fsm_map")
 231      - Various performance improvements
 232      - Vastly improved Xilinx flow
 233      - Added "make unsintall"
 234
 235  * Equivalence checking
 236      - Added equivalence checking commands:
 237          equiv_make equiv_simple equiv_status
 238          equiv_induct equiv_miter
 239          equiv_add equiv_remove
 240
 241  * Block RAM support:
 242      - Added "memory_bram" command
 243      - Added BRAM support to Xilinx flow
 244
 245  * Other New Commands and Options
 246      - Added "dff2dffe"
 247      - Added "fsm -encfile"
 248      - Added "dfflibmap -prepare"
 249      - Added "write_blid -unbuf -undef -blackbox"
 250      - Added "write_smt2" for writing SMT-LIBv2 files
 251      - Added "test_cell -w -muxdiv"
 252      - Added "select -read"
 253
 254
 255 Yosys 0.3.0 .. Yosys 0.4
 256 ------------------------
 257
 258  * Platform Support
 259      - Added support for mxe-based cross-builds for win32
 260      - Added sourcecode-export as VisualStudio project
 261      - Added experimental EMCC (JavaScript) support
 262
 263  * Verilog Frontend
 264      - Added -sv option for SystemVerilog (and automatic *.sv file support)
 265      - Added support for real-valued constants and constant expressions
 266      - Added support for non-standard "via_celltype" attribute on task/func
 267      - Added support for non-standard "module mod_name(...);" syntax
 268      - Added support for non-standard """ macro bodies
 269      - Added support for array with more than one dimension
 270      - Added support for $readmemh and $readmemb
 271      - Added support for DPI functions
 272
 273  * Changes in internal cell library
 274      - Added $shift and $shiftx cell types
 275      - Added $alu, $lcu, $fa and $macc cell types
 276      - Removed $bu0 and $safe_pmux cell types
 277      - $mem/$memwr WR_EN input is now a per-data-bit enable signal
 278      - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
 279      - Renamed ports of $lut cells (from I->O to A->Y)
 280      - Renamed $_INV_ to $_NOT_
 281
 282  * Changes for simple synthesis flows
 283      - There is now a "synth" command with a recommended default script
 284      - Many improvements in synthesis of arithmetic functions to gates
 285          - Multipliers and adders with many operands are using carry-save adder trees
 286          - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
 287      - Various new high-level optimizations on RTL netlist
 288      - Various improvements in FSM optimization
 289      - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
 290
 291  * Changes in internal APIs and RTLIL
 292      - Added log_id() and log_cell() helper functions
 293      - Added function-like cell creation helpers
 294      - Added GetSize() function (like .size() but with int)
 295      - Major refactoring of RTLIL::Module and related classes
 296      - Major refactoring of RTLIL::SigSpec and related classes
 297      - Now RTLIL::IdString is essentially an int
 298      - Added macros for code coverage counters
 299      - Added some Makefile magic for pretty make logs
 300      - Added "kernel/yosys.h" with all the core definitions
 301      - Changed a lot of code from FILE* to c++ streams
 302      - Added RTLIL::Monitor API and "trace" command
 303      - Added "Yosys" C++ namespace
 304
 305  * Changes relevant to SAT solving
 306      - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
 307      - Added native ezSAT support for vector shift ops
 308      - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
 309
 310  * New commands (or large improvements to commands)
 311      - Added "synth" command with default script
 312      - Added "share" (finally some real resource sharing)
 313      - Added "memory_share" (reduce number of ports on memories)
 314      - Added "wreduce" and "alumacc" commands
 315      - Added "opt -keepdc -fine -full -fast"
 316      - Added some "test_*" commands
 317
 318  * Various other changes
 319      - Added %D and %c select operators
 320      - Added support for labels in yosys scripts
 321      - Added support for here-documents in yosys scripts
 322      - Support "+/" prefix for files from proc_share_dir
 323      - Added "autoidx" statement to ilang language
 324      - Switched from "yosys-svgviewer" to "xdot"
 325      - Renamed "stdcells.v" to "techmap.v"
 326      - Various bug fixes and small improvements
 327      - Improved welcome and bye messages
 328
 329
 330 Yosys 0.2.0 .. Yosys 0.3.0
 331 --------------------------
 332
 333  * Driver program and overall behavior:
 334      - Added "design -push" and "design -pop"
 335      - Added "tee" command for redirecting log output
 336
 337  * Changes in the internal cell library:
 338      - Added $dlatchsr and $_DLATCHSR_???_ cell types
 339
 340  * Improvements in Verilog frontend:
 341      - Improved support for const functions (case, always, repeat)
 342      - The generate..endgenerate keywords are now optional
 343      - Added support for arrays of module instances
 344      - Added support for "`default_nettype" directive
 345      - Added support for "`line" directive
 346
 347  * Other front- and back-ends:
 348      - Various changes to "write_blif" options
 349      - Various improvements in EDIF backend
 350      - Added "vhdl2verilog" pseudo-front-end
 351      - Added "verific" pseudo-front-end
 352
 353  * Improvements in technology mapping:
 354      - Added support for recursive techmap
 355      - Added CONSTMSK and CONSTVAL features to techmap
 356      - Added _TECHMAP_CONNMAP_*_ feature to techmap
 357      - Added _TECHMAP_REPLACE_ feature to techmap
 358      - Added "connwrappers" command for wrap-extract-unwrap method
 359      - Added "extract -map %<design_name>" feature
 360      - Added "extract -ignore_param ..." and "extract -ignore_parameters"
 361      - Added "techmap -max_iter" option
 362
 363  * Improvements to "eval" and "sat" framework:
 364      - Now include a copy of Minisat (with build fixes applied)
 365      - Switched to Minisat::SimpSolver as SAT back-end
 366      - Added "sat -dump_vcd" feature
 367      - Added "sat -dump_cnf" feature
 368      - Added "sat -initsteps <N>" feature
 369      - Added "freduce -stop <N>" feature
 370      - Added "freduce -dump <prefix>" feature
 371
 372  * Integration with ABC:
 373      - Updated ABC rev to 7600ffb9340c
 374
 375  * Improvements in the internal APIs:
 376      - Added RTLIL::Module::add... helper methods
 377      - Various build fixes for OSX (Darwin) and OpenBSD
 378
 379
 380 Yosys 0.1.0 .. Yosys 0.2.0
 381 --------------------------
 382
 383  * Changes to the driver program:
 384      - Added "yosys -h" and "yosys -H"
 385      - Added support for backslash line continuation in scripts
 386      - Added support for #-comments in same line as command
 387      - Added "echo" and "log" commands
 388
 389  * Improvements in Verilog frontend:
 390      - Added support for local registers in named blocks
 391      - Added support for "case" in "generate" blocks
 392      - Added support for $clog2 system function
 393      - Added support for basic SystemVerilog assert statements
 394      - Added preprocessor support for macro arguments
 395      - Added preprocessor support for `elsif statement
 396      - Added "verilog_defaults" command
 397      - Added read_verilog -icells option
 398      - Added support for constant sizes from parameters
 399      - Added "read_verilog -setattr"
 400      - Added support for function returning 'integer'
 401      - Added limited support for function calls in parameter values
 402      - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
 403
 404  * Other front- and back-ends:
 405      - Added BTOR backend
 406      - Added Liberty frontend
 407
 408  * Improvements in technology mapping:
 409      - The "dfflibmap" command now strongly prefers solutions with
 410            no inverters in clock paths
 411      - The "dfflibmap" command now prefers cells with smaller area
 412      - Added support for multiple -map options to techmap
 413      - Added "dfflibmap" support for //-comments in liberty files
 414      - Added "memory_unpack" command to revert "memory_collect"
 415      - Added standard techmap rule "techmap -share_map pmux2mux.v"
 416      - Added "iopadmap -bits"
 417      - Added "setundef" command
 418      - Added "hilomap" command
 419
 420  * Changes in the internal cell library:
 421      - Major rewrite of simlib.v for better compatibility with other tools
 422      - Added PRIORITY parameter to $memwr cells
 423      - Added TRANSPARENT parameter to $memrd cells
 424      - Added RD_TRANSPARENT parameter to $mem cells
 425      - Added $bu0 cell (always 0-extend, even undef MSB)
 426      - Added $assert cell type
 427      - Added $slice and $concat cell types
 428
 429  * Integration with ABC:
 430      - Updated ABC to hg rev 2058c8ccea68
 431      - Tighter integration of ABC build with Yosys build. The make
 432            targets 'make abc' and 'make install-abc' are now obsolete.
 433      - Added support for passing FFs from one clock domain through ABC
 434      - Now always use BLIF as exchange format with ABC
 435      - Added support for "abc -script +<command_sequence>"
 436      - Improved standard ABC recipe
 437      - Added support for "keep" attribute to abc command
 438      - Added "abc -dff / -clk / -keepff" options
 439
 440  * Improvements to "eval" and "sat" framework:
 441      - Added support for "0" and "~0" in right-hand side -set expressions
 442      - Added "eval -set-undef" and "eval -table"
 443      - Added "sat -set-init" and "sat -set-init-*" for sequential problems
 444      - Added undef support to SAT solver, incl. various new "sat" options
 445      - Added correct support for === and !== for "eval" and "sat"
 446      - Added "sat -tempinduct" (default -seq is now non-induction sequential)
 447      - Added "sat -prove-asserts"
 448      - Complete rewrite of the 'freduce' command
 449      - Added "miter" command
 450      - Added "sat -show-inputs" and "sat -show-outputs"
 451      - Added "sat -ignore_unknown_cells" (now produce an error by default)
 452      - Added "sat -falsify"
 453      - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
 454      - Added "expose" command
 455      - Added support for @<sel_name> to sat and eval signal expressions
 456
 457  * Changes in the 'make test' framework and auxiliary test tools:
 458      - Added autotest.sh -p and -f options
 459      - Replaced autotest.sh ISIM support with XSIM support
 460      - Added test cases for SAT framework
 461
 462  * Added "abbreviated IDs":
 463      - Now $<something>$foo can be abbreviated as $foo.
 464      - Usually this last part is a unique id (from RTLIL::autoidx)
 465      - This abbreviated IDs are now also used in "show" output
 466
 467  * Other changes to selection framework:
 468      - Now */ is optional in */<mode>:<arg> expressions
 469      - Added "select -assert-none" and "select -assert-any"
 470      - Added support for matching modules by attribute (A:<expr>)
 471      - Added "select -none"
 472      - Added support for r:<expr> pattern for matching cell parameters
 473      - Added support for !=, <, <=, >=, > for attribute and parameter matching
 474      - Added support for %s for selecting sub-modules
 475      - Added support for %m for expanding selections to whole modules
 476      - Added support for i:*, o:* and x:* pattern for selecting module ports
 477      - Added support for s:<expr> pattern for matching wire width
 478      - Added support for %a operation to select wire aliases
 479
 480  * Various other changes to commands and options:
 481      - The "ls" command now supports wildcards
 482      - Added "show -pause" and "show -format dot"
 483      - Added "show -color" support for cells
 484      - Added "show -label" and "show -notitle"
 485      - Added "dump -m" and "dump -n"
 486      - Added "history" command
 487      - Added "rename -hide"
 488      - Added "connect" command
 489      - Added "splitnets -driver"
 490      - Added "opt_const -mux_undef"
 491      - Added "opt_const -mux_bool"
 492      - Added "opt_const -undriven"
 493      - Added "opt -mux_undef -mux_bool -undriven -purge"
 494      - Added "hierarchy -libdir"
 495      - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
 496      - Added "delete" command
 497      - Added "dump -append"
 498      - Added "setattr" and "setparam" commands
 499      - Added "design -stash/-copy-from/-copy-to"
 500      - Added "copy" command
 501      - Added "splice" command
 502