CHANGELOG

   1
   2 List of major changes and improvements between releases
   3 =======================================================
   4
   5
   6 Yosys 0.9 .. Yosys 0.9-dev
   7 --------------------------
   8
   9  * Various
  10     - Added "write_xaiger" backend
  11     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
  12     - Added "synth_xilinx -abc9" (experimental)
  13     - Added "synth_ice40 -abc9" (experimental)
  14     - Added "synth -abc9" (experimental)
  15     - Added "script -scriptwire
  16     - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
  17     - Renamed labels/options in synth_ice40 (e.g. map_dram -> map_lutram; -nodram -> -nolutram)
  18     - Renamed labels/options in synth_ecp5 (e.g. map_dram -> map_lutram; -nodram -> -nolutram)
  19     - Renamed labels/options in synth_xilinx (e.g. map_dram -> map_lutram; -nodram -> -nolutram)
  20
  21
  22 Yosys 0.8 .. Yosys 0.8-dev
  23 --------------------------
  24
  25  * Various
  26     - Added $changed support to read_verilog
  27     - Added "write_edif -attrprop"
  28     - Added "ice40_unlut" pass
  29     - Added "opt_lut" pass
  30     - Added "synth_ice40 -relut"
  31     - Added "synth_ice40 -noabc"
  32     - Added "gate2lut.v" techmap rule
  33     - Added "rename -src"
  34     - Added "equiv_opt" pass
  35     - Added "shregmap -tech xilinx"
  36     - Added "read_aiger" frontend
  37     - Added "muxcover -mux{4,8,16}=<cost>"
  38     - Added "muxcover -dmux=<cost>"
  39     - Added "muxcover -nopartial"
  40     - Added "muxpack" pass
  41     - Added "pmux2shiftx -norange"
  42     - Added "synth_xilinx -nocarry"
  43     - Added "synth_xilinx -nowidelut"
  44     - Added "synth_ecp5 -nowidelut"
  45     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
  46     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
  47
  48
  49 Yosys 0.7 .. Yosys 0.8
  50 ----------------------
  51
  52  * Various
  53     - Many bugfixes and small improvements
  54     - Strip debug symbols from installed binary
  55     - Replace -ignore_redef with -[no]overwrite in front-ends
  56     - Added write_verilog hex dump support, add -nohex option
  57     - Added "write_verilog -decimal"
  58     - Added "scc -set_attr"
  59     - Added "verilog_defines" command
  60     - Remember defines from one read_verilog to next
  61     - Added support for hierarchical defparam
  62     - Added FIRRTL back-end
  63     - Improved ABC default scripts
  64     - Added "design -reset-vlog"
  65     - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
  66     - Added Verilog $rtoi and $itor support
  67     - Added "check -initdrv"
  68     - Added "read_blif -wideports"
  69     - Added support for SystemVerilog "++" and "--" operators
  70     - Added support for SystemVerilog unique, unique0, and priority case
  71     - Added "write_edif" options for edif "flavors"
  72     - Added support for resetall compiler directive
  73     - Added simple C beck-end (bitwise combinatorical only atm)
  74     - Added $_ANDNOT_ and $_ORNOT_ cell types
  75     - Added cell library aliases to "abc -g"
  76     - Added "setundef -anyseq"
  77     - Added "chtype" command
  78     - Added "design -import"
  79     - Added "write_table" command
  80     - Added "read_json" command
  81     - Added "sim" command
  82     - Added "extract_fa" and "extract_reduce" commands
  83     - Added "extract_counter" command
  84     - Added "opt_demorgan" command
  85     - Added support for $size and $bits SystemVerilog functions
  86     - Added "blackbox" command
  87     - Added "ltp" command
  88     - Added support for editline as replacement for readline
  89     - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
  90     - Added "yosys -E" for creating Makefile dependencies files
  91     - Added "synth -noshare"
  92     - Added "memory_nordff"
  93     - Added "setundef -undef -expose -anyconst"
  94     - Added "expose -input"
  95     - Added specify/specparam parser support (simply ignore them)
  96     - Added "write_blif -inames -iattr"
  97     - Added "hierarchy -simcheck"
  98     - Added an option to statically link abc into yosys
  99     - Added protobuf back-end
 100     - Added BLIF parsing support for .conn and .cname
 101     - Added read_verilog error checking for reg/wire/logic misuse
 102     - Added "make coverage" and ENABLE_GCOV build option
 103
 104  * Changes in Yosys APIs
 105     - Added ConstEval defaultval feature
 106     - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
 107     - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
 108     - Added log_file_warning() and log_file_error() functions
 109
 110  * Formal Verification
 111     - Added "write_aiger"
 112     - Added "yosys-smtbmc --aig"
 113     - Added "always <positive_int>" to .smtc format
 114     - Added $cover cell type and support for cover properties
 115     - Added $fair/$live cell type and support for liveness properties
 116     - Added smtbmc support for memory vcd dumping
 117     - Added "chformal" command
 118     - Added "write_smt2 -stbv" and "write_smt2 -stdt"
 119     - Fix equiv_simple, old behavior now available with "equiv_simple -short"
 120     - Change to Yices2 as default SMT solver (it is GPL now)
 121     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
 122     - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
 123     - Added a brand new "write_btor" command for BTOR2
 124     - Added clk2fflogic memory support and other improvements
 125     - Added "async memory write" support to write_smt2
 126     - Simulate clock toggling in yosys-smtbmc VCD output
 127     - Added $allseq/$allconst cells for EA-solving
 128     - Make -nordff the default in "prep"
 129     - Added (* gclk *) attribute
 130     - Added "async2sync" pass for single-clock designs with async resets
 131
 132  * Verific support
 133     - Many improvements in Verific front-end
 134     - Added proper handling of concurent SVA properties
 135     - Map "const" and "rand const" to $anyseq/$anyconst
 136     - Added "verific -import -flatten" and "verific -import -extnets"
 137     - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
 138     - Remove PSL support (because PSL has been removed in upstream Verific)
 139     - Improve integration with "hierarchy" command design elaboration
 140     - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
 141     - Added simpilied "read" command that automatically uses verific if available
 142     - Added "verific -set-<severity> <msg_id>.."
 143     - Added "verific -work <libname>"
 144
 145  * New back-ends
 146     - Added initial Coolrunner-II support
 147     - Added initial eASIC support
 148     - Added initial ECP5 support
 149
 150  * GreenPAK Support
 151     - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
 152
 153  * iCE40 Support
 154     - Add "synth_ice40 -vpr"
 155     - Add "synth_ice40 -nodffe"
 156     - Add "synth_ice40 -json"
 157     - Add Support for UltraPlus cells
 158
 159  * MAX10 and Cyclone IV Support
 160     - Added initial version of metacommand "synth_intel".
 161     - Improved write_verilog command to produce VQM netlist for Quartus Prime.
 162     - Added support for MAX10 FPGA family synthesis.
 163     - Added support for Cyclone IV family synthesis.
 164     - Added example of implementation for DE2i-150 board.
 165     - Added example of implementation for MAX10 development kit.
 166     - Added LFSR example from Asic World.
 167     - Added "dffinit -highlow" for mapping to Intel primitives
 168
 169
 170 Yosys 0.6 .. Yosys 0.7
 171 ----------------------
 172
 173  * Various
 174     - Added "yosys -D" feature
 175     - Added support for installed plugins in $(DATDIR)/plugins/
 176     - Renamed opt_const to opt_expr
 177     - Renamed opt_share to opt_merge
 178     - Added "prep -flatten" and "synth -flatten"
 179     - Added "prep -auto-top" and "synth -auto-top"
 180     - Using "mfs" and "lutpack" in ABC lut mapping
 181     - Support for abstract modules in chparam
 182     - Cleanup abstract modules at end of "hierarchy -top"
 183     - Added tristate buffer support to iopadmap
 184     - Added opt_expr support for div/mod by power-of-two
 185     - Added "select -assert-min <N> -assert-max <N>"
 186     - Added "attrmvcp" pass
 187     - Added "attrmap" command
 188     - Added "tee +INT -INT"
 189     - Added "zinit" pass
 190     - Added "setparam -type"
 191     - Added "shregmap" pass
 192     - Added "setundef -init"
 193     - Added "nlutmap -assert"
 194     - Added $sop cell type and "abc -sop -I <num> -P <num>"
 195     - Added "dc2" to default ABC scripts
 196     - Added "deminout"
 197     - Added "insbuf" command
 198     - Added "prep -nomem"
 199     - Added "opt_rmdff -keepdc"
 200     - Added "prep -nokeepdc"
 201     - Added initial version of "synth_gowin"
 202     - Added "fsm_expand -full"
 203     - Added support for fsm_encoding="user"
 204     - Many improvements in GreenPAK4 support
 205     - Added black box modules for all Xilinx 7-series lib cells
 206     - Added synth_ice40 support for latches via logic loops
 207     - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
 208
 209  * Build System
 210     - Added ABCEXTERNAL and ABCURL make variables
 211     - Added BINDIR, LIBDIR, and DATDIR make variables
 212     - Added PKG_CONFIG make variable
 213     - Added SEED make variable (for "make test")
 214     - Added YOSYS_VER_STR make variable
 215     - Updated min GCC requirement to GCC 4.8
 216     - Updated required Bison version to Bison 3.x
 217
 218  * Internal APIs
 219     - Added ast.h to exported headers
 220     - Added ScriptPass helper class for script-like passes
 221     - Added CellEdgesDatabase API
 222
 223  * Front-ends and Back-ends
 224     - Added filename glob support to all front-ends
 225     - Added avail (black-box) module params to ilang format
 226     - Added $display %m support
 227     - Added support for $stop Verilog system task
 228     - Added support for SystemVerilog packages
 229     - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
 230     - Added support for "active high" and "active low" latches in read_blif and write_blif
 231     - Use init value "2" for all uninitialized FFs in BLIF back-end
 232     - Added "read_blif -sop"
 233     - Added "write_blif -noalias"
 234     - Added various write_blif options for VTR support
 235     - write_json: also write module attributes.
 236     - Added "write_verilog -nodec -nostr -defparam"
 237     - Added "read_verilog -norestrict -assume-asserts"
 238     - Added support for bus interfaces to "read_liberty -lib"
 239     - Added liberty parser support for types within cell decls
 240     - Added "write_verilog -renameprefix -v"
 241     - Added "write_edif -nogndvcc"
 242
 243  * Formal Verification
 244     - Support for hierarchical designs in smt2 back-end
 245     - Yosys-smtbmc: Support for hierarchical VCD dumping
 246     - Added $initstate cell type and vlog function
 247     - Added $anyconst and $anyseq cell types and vlog functions
 248     - Added printing of code loc of failed asserts to yosys-smtbmc
 249     - Added memory_memx pass, "memory -memx", and "prep -memx"
 250     - Added "proc_mux -ifx"
 251     - Added "yosys-smtbmc -g"
 252     - Deprecated "write_smt2 -regs" (by default on now)
 253     - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
 254     - Added support for memories to smtio.py
 255     - Added "yosys-smtbmc --dump-vlogtb"
 256     - Added "yosys-smtbmc --smtc --dump-smtc"
 257     - Added "yosys-smtbmc --dump-all"
 258     - Added assertpmux command
 259     - Added "yosys-smtbmc --unroll"
 260     - Added $past, $stable, $rose, $fell SVA functions
 261     - Added "yosys-smtbmc --noinfo and --dummy"
 262     - Added "yosys-smtbmc --noincr"
 263     - Added "yosys-smtbmc --cex <filename>"
 264     - Added $ff and $_FF_ cell types
 265     - Added $global_clock verilog syntax support for creating $ff cells
 266     - Added clk2fflogic
 267
 268
 269 Yosys 0.5 .. Yosys 0.6
 270 ----------------------
 271
 272  * Various
 273      - Added Contributor Covenant Code of Conduct
 274      - Various improvements in dict<> and pool<>
 275      - Added hashlib::mfp and refactored SigMap
 276      - Improved support for reals as module parameters
 277      - Various improvements in SMT2 back-end
 278      - Added "keep_hierarchy" attribute
 279      - Verilog front-end: define `BLACKBOX in -lib mode
 280      - Added API for converting internal cells to AIGs
 281      - Added ENABLE_LIBYOSYS Makefile option
 282      - Removed "techmap -share_map" (use "-map +/filename" instead)
 283      - Switched all Python scripts to Python 3
 284      - Added support for $display()/$write() and $finish() to Verilog front-end
 285      - Added "yosys-smtbmc" formal verification flow
 286      - Added options for clang sanitizers to Makefile
 287
 288  * New commands and options
 289      - Added "scc -expect <N> -nofeedback"
 290      - Added "proc_dlatch"
 291      - Added "check"
 292      - Added "select %xe %cie %coe %M %C %R"
 293      - Added "sat -dump_json" (WaveJSON format)
 294      - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
 295      - Added "sat -stepsize" and "sat -tempinduct-step"
 296      - Added "sat -show-regs -show-public -show-all"
 297      - Added "write_json" (Native Yosys JSON format)
 298      - Added "write_blif -attr"
 299      - Added "dffinit"
 300      - Added "chparam"
 301      - Added "muxcover"
 302      - Added "pmuxtree"
 303      - Added memory_bram "make_outreg" feature
 304      - Added "splice -wires"
 305      - Added "dff2dffe -direct-match"
 306      - Added simplemap $lut support
 307      - Added "read_blif"
 308      - Added "opt_share -share_all"
 309      - Added "aigmap"
 310      - Added "write_smt2 -mem -regs -wires"
 311      - Added "memory -nordff"
 312      - Added "write_smv"
 313      - Added "synth -nordff -noalumacc"
 314      - Added "rename -top new_name"
 315      - Added "opt_const -clkinv"
 316      - Added "synth -nofsm"
 317      - Added "miter -assert"
 318      - Added "read_verilog -noautowire"
 319      - Added "read_verilog -nodpi"
 320      - Added "tribuf"
 321      - Added "lut2mux"
 322      - Added "nlutmap"
 323      - Added "qwp"
 324      - Added "test_cell -noeval"
 325      - Added "edgetypes"
 326      - Added "equiv_struct"
 327      - Added "equiv_purge"
 328      - Added "equiv_mark"
 329      - Added "equiv_add -try -cell"
 330      - Added "singleton"
 331      - Added "abc -g -luts"
 332      - Added "torder"
 333      - Added "write_blif -cname"
 334      - Added "submod -copy"
 335      - Added "dffsr2dff"
 336      - Added "stat -liberty"
 337
 338  * Synthesis metacommands
 339      - Various improvements in synth_xilinx
 340      - Added synth_ice40 and synth_greenpak4
 341      - Added "prep" metacommand for "synthesis lite"
 342
 343  * Cell library changes
 344      - Added cell types to "help" system
 345      - Added $meminit cell type
 346      - Added $assume cell type
 347      - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
 348      - Added $tribuf and $_TBUF_ cell types
 349      - Added read-enable to memory model
 350
 351  * YosysJS
 352      - Various improvements in emscripten build
 353      - Added alternative webworker-based JS API
 354      - Added a few example applications
 355
 356
 357 Yosys 0.4 .. Yosys 0.5
 358 ----------------------
 359
 360  * API changes
 361      - Added log_warning()
 362      - Added eval_select_args() and eval_select_op()
 363      - Added cell->known(), cell->input(portname), cell->output(portname)
 364      - Skip blackbox modules in design->selected_modules()
 365      - Replaced std::map<> and std::set<> with dict<> and pool<>
 366      - New SigSpec::extend() is what used to be SigSpec::extend_u0()
 367      - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
 368
 369  * Cell library changes
 370      - Added flip-flops with enable ($dffe etc.)
 371      - Added $equiv cells for equivalence checking framework
 372
 373  * Various
 374      - Updated ABC to hg rev 61ad5f908c03
 375      - Added clock domain partitioning to ABC pass
 376      - Improved plugin building (see "yosys-config --build")
 377      - Added ENABLE_NDEBUG Makefile flag for high-performance builds
 378      - Added "yosys -d", "yosys -L" and other driver improvements
 379      - Added support for multi-bit (array) cell ports to "write_edif"
 380      - Now printing most output to stdout, not stderr
 381      - Added "onehot" attribute (set by "fsm_map")
 382      - Various performance improvements
 383      - Vastly improved Xilinx flow
 384      - Added "make unsintall"
 385
 386  * Equivalence checking
 387      - Added equivalence checking commands:
 388          equiv_make equiv_simple equiv_status
 389          equiv_induct equiv_miter
 390          equiv_add equiv_remove
 391
 392  * Block RAM support:
 393      - Added "memory_bram" command
 394      - Added BRAM support to Xilinx flow
 395
 396  * Other New Commands and Options
 397      - Added "dff2dffe"
 398      - Added "fsm -encfile"
 399      - Added "dfflibmap -prepare"
 400      - Added "write_blid -unbuf -undef -blackbox"
 401      - Added "write_smt2" for writing SMT-LIBv2 files
 402      - Added "test_cell -w -muxdiv"
 403      - Added "select -read"
 404
 405
 406 Yosys 0.3.0 .. Yosys 0.4
 407 ------------------------
 408
 409  * Platform Support
 410      - Added support for mxe-based cross-builds for win32
 411      - Added sourcecode-export as VisualStudio project
 412      - Added experimental EMCC (JavaScript) support
 413
 414  * Verilog Frontend
 415      - Added -sv option for SystemVerilog (and automatic *.sv file support)
 416      - Added support for real-valued constants and constant expressions
 417      - Added support for non-standard "via_celltype" attribute on task/func
 418      - Added support for non-standard "module mod_name(...);" syntax
 419      - Added support for non-standard """ macro bodies
 420      - Added support for array with more than one dimension
 421      - Added support for $readmemh and $readmemb
 422      - Added support for DPI functions
 423
 424  * Changes in internal cell library
 425      - Added $shift and $shiftx cell types
 426      - Added $alu, $lcu, $fa and $macc cell types
 427      - Removed $bu0 and $safe_pmux cell types
 428      - $mem/$memwr WR_EN input is now a per-data-bit enable signal
 429      - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
 430      - Renamed ports of $lut cells (from I->O to A->Y)
 431      - Renamed $_INV_ to $_NOT_
 432
 433  * Changes for simple synthesis flows
 434      - There is now a "synth" command with a recommended default script
 435      - Many improvements in synthesis of arithmetic functions to gates
 436          - Multipliers and adders with many operands are using carry-save adder trees
 437          - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
 438      - Various new high-level optimizations on RTL netlist
 439      - Various improvements in FSM optimization
 440      - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
 441
 442  * Changes in internal APIs and RTLIL
 443      - Added log_id() and log_cell() helper functions
 444      - Added function-like cell creation helpers
 445      - Added GetSize() function (like .size() but with int)
 446      - Major refactoring of RTLIL::Module and related classes
 447      - Major refactoring of RTLIL::SigSpec and related classes
 448      - Now RTLIL::IdString is essentially an int
 449      - Added macros for code coverage counters
 450      - Added some Makefile magic for pretty make logs
 451      - Added "kernel/yosys.h" with all the core definitions
 452      - Changed a lot of code from FILE* to c++ streams
 453      - Added RTLIL::Monitor API and "trace" command
 454      - Added "Yosys" C++ namespace
 455
 456  * Changes relevant to SAT solving
 457      - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
 458      - Added native ezSAT support for vector shift ops
 459      - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
 460
 461  * New commands (or large improvements to commands)
 462      - Added "synth" command with default script
 463      - Added "share" (finally some real resource sharing)
 464      - Added "memory_share" (reduce number of ports on memories)
 465      - Added "wreduce" and "alumacc" commands
 466      - Added "opt -keepdc -fine -full -fast"
 467      - Added some "test_*" commands
 468
 469  * Various other changes
 470      - Added %D and %c select operators
 471      - Added support for labels in yosys scripts
 472      - Added support for here-documents in yosys scripts
 473      - Support "+/" prefix for files from proc_share_dir
 474      - Added "autoidx" statement to ilang language
 475      - Switched from "yosys-svgviewer" to "xdot"
 476      - Renamed "stdcells.v" to "techmap.v"
 477      - Various bug fixes and small improvements
 478      - Improved welcome and bye messages
 479
 480
 481 Yosys 0.2.0 .. Yosys 0.3.0
 482 --------------------------
 483
 484  * Driver program and overall behavior:
 485      - Added "design -push" and "design -pop"
 486      - Added "tee" command for redirecting log output
 487
 488  * Changes in the internal cell library:
 489      - Added $dlatchsr and $_DLATCHSR_???_ cell types
 490
 491  * Improvements in Verilog frontend:
 492      - Improved support for const functions (case, always, repeat)
 493      - The generate..endgenerate keywords are now optional
 494      - Added support for arrays of module instances
 495      - Added support for "`default_nettype" directive
 496      - Added support for "`line" directive
 497
 498  * Other front- and back-ends:
 499      - Various changes to "write_blif" options
 500      - Various improvements in EDIF backend
 501      - Added "vhdl2verilog" pseudo-front-end
 502      - Added "verific" pseudo-front-end
 503
 504  * Improvements in technology mapping:
 505      - Added support for recursive techmap
 506      - Added CONSTMSK and CONSTVAL features to techmap
 507      - Added _TECHMAP_CONNMAP_*_ feature to techmap
 508      - Added _TECHMAP_REPLACE_ feature to techmap
 509      - Added "connwrappers" command for wrap-extract-unwrap method
 510      - Added "extract -map %<design_name>" feature
 511      - Added "extract -ignore_param ..." and "extract -ignore_parameters"
 512      - Added "techmap -max_iter" option
 513
 514  * Improvements to "eval" and "sat" framework:
 515      - Now include a copy of Minisat (with build fixes applied)
 516      - Switched to Minisat::SimpSolver as SAT back-end
 517      - Added "sat -dump_vcd" feature
 518      - Added "sat -dump_cnf" feature
 519      - Added "sat -initsteps <N>" feature
 520      - Added "freduce -stop <N>" feature
 521      - Added "freduce -dump <prefix>" feature
 522
 523  * Integration with ABC:
 524      - Updated ABC rev to 7600ffb9340c
 525
 526  * Improvements in the internal APIs:
 527      - Added RTLIL::Module::add... helper methods
 528      - Various build fixes for OSX (Darwin) and OpenBSD
 529
 530
 531 Yosys 0.1.0 .. Yosys 0.2.0
 532 --------------------------
 533
 534  * Changes to the driver program:
 535      - Added "yosys -h" and "yosys -H"
 536      - Added support for backslash line continuation in scripts
 537      - Added support for #-comments in same line as command
 538      - Added "echo" and "log" commands
 539
 540  * Improvements in Verilog frontend:
 541      - Added support for local registers in named blocks
 542      - Added support for "case" in "generate" blocks
 543      - Added support for $clog2 system function
 544      - Added support for basic SystemVerilog assert statements
 545      - Added preprocessor support for macro arguments
 546      - Added preprocessor support for `elsif statement
 547      - Added "verilog_defaults" command
 548      - Added read_verilog -icells option
 549      - Added support for constant sizes from parameters
 550      - Added "read_verilog -setattr"
 551      - Added support for function returning 'integer'
 552      - Added limited support for function calls in parameter values
 553      - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
 554
 555  * Other front- and back-ends:
 556      - Added BTOR backend
 557      - Added Liberty frontend
 558
 559  * Improvements in technology mapping:
 560      - The "dfflibmap" command now strongly prefers solutions with
 561            no inverters in clock paths
 562      - The "dfflibmap" command now prefers cells with smaller area
 563      - Added support for multiple -map options to techmap
 564      - Added "dfflibmap" support for //-comments in liberty files
 565      - Added "memory_unpack" command to revert "memory_collect"
 566      - Added standard techmap rule "techmap -share_map pmux2mux.v"
 567      - Added "iopadmap -bits"
 568      - Added "setundef" command
 569      - Added "hilomap" command
 570
 571  * Changes in the internal cell library:
 572      - Major rewrite of simlib.v for better compatibility with other tools
 573      - Added PRIORITY parameter to $memwr cells
 574      - Added TRANSPARENT parameter to $memrd cells
 575      - Added RD_TRANSPARENT parameter to $mem cells
 576      - Added $bu0 cell (always 0-extend, even undef MSB)
 577      - Added $assert cell type
 578      - Added $slice and $concat cell types
 579
 580  * Integration with ABC:
 581      - Updated ABC to hg rev 2058c8ccea68
 582      - Tighter integration of ABC build with Yosys build. The make
 583            targets 'make abc' and 'make install-abc' are now obsolete.
 584      - Added support for passing FFs from one clock domain through ABC
 585      - Now always use BLIF as exchange format with ABC
 586      - Added support for "abc -script +<command_sequence>"
 587      - Improved standard ABC recipe
 588      - Added support for "keep" attribute to abc command
 589      - Added "abc -dff / -clk / -keepff" options
 590
 591  * Improvements to "eval" and "sat" framework:
 592      - Added support for "0" and "~0" in right-hand side -set expressions
 593      - Added "eval -set-undef" and "eval -table"
 594      - Added "sat -set-init" and "sat -set-init-*" for sequential problems
 595      - Added undef support to SAT solver, incl. various new "sat" options
 596      - Added correct support for === and !== for "eval" and "sat"
 597      - Added "sat -tempinduct" (default -seq is now non-induction sequential)
 598      - Added "sat -prove-asserts"
 599      - Complete rewrite of the 'freduce' command
 600      - Added "miter" command
 601      - Added "sat -show-inputs" and "sat -show-outputs"
 602      - Added "sat -ignore_unknown_cells" (now produce an error by default)
 603      - Added "sat -falsify"
 604      - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
 605      - Added "expose" command
 606      - Added support for @<sel_name> to sat and eval signal expressions
 607
 608  * Changes in the 'make test' framework and auxiliary test tools:
 609      - Added autotest.sh -p and -f options
 610      - Replaced autotest.sh ISIM support with XSIM support
 611      - Added test cases for SAT framework
 612
 613  * Added "abbreviated IDs":
 614      - Now $<something>$foo can be abbreviated as $foo.
 615      - Usually this last part is a unique id (from RTLIL::autoidx)
 616      - This abbreviated IDs are now also used in "show" output
 617
 618  * Other changes to selection framework:
 619      - Now */ is optional in */<mode>:<arg> expressions
 620      - Added "select -assert-none" and "select -assert-any"
 621      - Added support for matching modules by attribute (A:<expr>)
 622      - Added "select -none"
 623      - Added support for r:<expr> pattern for matching cell parameters
 624      - Added support for !=, <, <=, >=, > for attribute and parameter matching
 625      - Added support for %s for selecting sub-modules
 626      - Added support for %m for expanding selections to whole modules
 627      - Added support for i:*, o:* and x:* pattern for selecting module ports
 628      - Added support for s:<expr> pattern for matching wire width
 629      - Added support for %a operation to select wire aliases
 630
 631  * Various other changes to commands and options:
 632      - The "ls" command now supports wildcards
 633      - Added "show -pause" and "show -format dot"
 634      - Added "show -color" support for cells
 635      - Added "show -label" and "show -notitle"
 636      - Added "dump -m" and "dump -n"
 637      - Added "history" command
 638      - Added "rename -hide"
 639      - Added "connect" command
 640      - Added "splitnets -driver"
 641      - Added "opt_const -mux_undef"
 642      - Added "opt_const -mux_bool"
 643      - Added "opt_const -undriven"
 644      - Added "opt -mux_undef -mux_bool -undriven -purge"
 645      - Added "hierarchy -libdir"
 646      - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
 647      - Added "delete" command
 648      - Added "dump -append"
 649      - Added "setattr" and "setparam" commands
 650      - Added "design -stash/-copy-from/-copy-to"
 651      - Added "copy" command
 652      - Added "splice" command
 653