Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
[yosys.git] / CHANGELOG
1
2 List of major changes and improvements between releases
3 =======================================================
4
5
6 Yosys 0.9 .. Yosys 0.9-dev
7 --------------------------
8
9 * Various
10 - Added "write_xaiger" backend
11 - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
12 - Added "synth_xilinx -abc9" (experimental)
13 - Added "synth_ice40 -abc9" (experimental)
14 - Added "synth -abc9" (experimental)
15 - Added "script -scriptwire
16 - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
17 - Added automatic gzip decompression for frontends
18 - Added $_NMUX_ cell type
19 - Added automatic gzip compression (based on filename extension) for backends
20 - Improve attribute and parameter encoding in JSON to avoid ambiguities between
21 bit vectors and strings containing [01xz]*
22 - Added "clkbufmap" pass
23 - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
24 - Added "synth_xilinx -ise" (experimental)
25 - Added "synth_xilinx -iopad"
26 - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
27
28 Yosys 0.8 .. Yosys 0.8-dev
29 --------------------------
30
31 * Various
32 - Added $changed support to read_verilog
33 - Added "write_edif -attrprop"
34 - Added "ice40_unlut" pass
35 - Added "opt_lut" pass
36 - Added "synth_ice40 -relut"
37 - Added "synth_ice40 -noabc"
38 - Added "gate2lut.v" techmap rule
39 - Added "rename -src"
40 - Added "equiv_opt" pass
41 - Added "shregmap -tech xilinx"
42 - Added "read_aiger" frontend
43 - Added "muxcover -mux{4,8,16}=<cost>"
44 - Added "muxcover -dmux=<cost>"
45 - Added "muxcover -nopartial"
46 - Added "muxpack" pass
47 - Added "pmux2shiftx -norange"
48 - Added "synth_xilinx -nocarry"
49 - Added "synth_xilinx -nowidelut"
50 - Added "synth_ecp5 -nowidelut"
51 - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
52 - Fixed sign extension of unsized constants with 'bx and 'bz MSB
53
54
55 Yosys 0.7 .. Yosys 0.8
56 ----------------------
57
58 * Various
59 - Many bugfixes and small improvements
60 - Strip debug symbols from installed binary
61 - Replace -ignore_redef with -[no]overwrite in front-ends
62 - Added write_verilog hex dump support, add -nohex option
63 - Added "write_verilog -decimal"
64 - Added "scc -set_attr"
65 - Added "verilog_defines" command
66 - Remember defines from one read_verilog to next
67 - Added support for hierarchical defparam
68 - Added FIRRTL back-end
69 - Improved ABC default scripts
70 - Added "design -reset-vlog"
71 - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
72 - Added Verilog $rtoi and $itor support
73 - Added "check -initdrv"
74 - Added "read_blif -wideports"
75 - Added support for SystemVerilog "++" and "--" operators
76 - Added support for SystemVerilog unique, unique0, and priority case
77 - Added "write_edif" options for edif "flavors"
78 - Added support for resetall compiler directive
79 - Added simple C beck-end (bitwise combinatorical only atm)
80 - Added $_ANDNOT_ and $_ORNOT_ cell types
81 - Added cell library aliases to "abc -g"
82 - Added "setundef -anyseq"
83 - Added "chtype" command
84 - Added "design -import"
85 - Added "write_table" command
86 - Added "read_json" command
87 - Added "sim" command
88 - Added "extract_fa" and "extract_reduce" commands
89 - Added "extract_counter" command
90 - Added "opt_demorgan" command
91 - Added support for $size and $bits SystemVerilog functions
92 - Added "blackbox" command
93 - Added "ltp" command
94 - Added support for editline as replacement for readline
95 - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
96 - Added "yosys -E" for creating Makefile dependencies files
97 - Added "synth -noshare"
98 - Added "memory_nordff"
99 - Added "setundef -undef -expose -anyconst"
100 - Added "expose -input"
101 - Added specify/specparam parser support (simply ignore them)
102 - Added "write_blif -inames -iattr"
103 - Added "hierarchy -simcheck"
104 - Added an option to statically link abc into yosys
105 - Added protobuf back-end
106 - Added BLIF parsing support for .conn and .cname
107 - Added read_verilog error checking for reg/wire/logic misuse
108 - Added "make coverage" and ENABLE_GCOV build option
109
110 * Changes in Yosys APIs
111 - Added ConstEval defaultval feature
112 - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
113 - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
114 - Added log_file_warning() and log_file_error() functions
115
116 * Formal Verification
117 - Added "write_aiger"
118 - Added "yosys-smtbmc --aig"
119 - Added "always <positive_int>" to .smtc format
120 - Added $cover cell type and support for cover properties
121 - Added $fair/$live cell type and support for liveness properties
122 - Added smtbmc support for memory vcd dumping
123 - Added "chformal" command
124 - Added "write_smt2 -stbv" and "write_smt2 -stdt"
125 - Fix equiv_simple, old behavior now available with "equiv_simple -short"
126 - Change to Yices2 as default SMT solver (it is GPL now)
127 - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
128 - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
129 - Added a brand new "write_btor" command for BTOR2
130 - Added clk2fflogic memory support and other improvements
131 - Added "async memory write" support to write_smt2
132 - Simulate clock toggling in yosys-smtbmc VCD output
133 - Added $allseq/$allconst cells for EA-solving
134 - Make -nordff the default in "prep"
135 - Added (* gclk *) attribute
136 - Added "async2sync" pass for single-clock designs with async resets
137
138 * Verific support
139 - Many improvements in Verific front-end
140 - Added proper handling of concurent SVA properties
141 - Map "const" and "rand const" to $anyseq/$anyconst
142 - Added "verific -import -flatten" and "verific -import -extnets"
143 - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
144 - Remove PSL support (because PSL has been removed in upstream Verific)
145 - Improve integration with "hierarchy" command design elaboration
146 - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
147 - Added simpilied "read" command that automatically uses verific if available
148 - Added "verific -set-<severity> <msg_id>.."
149 - Added "verific -work <libname>"
150
151 * New back-ends
152 - Added initial Coolrunner-II support
153 - Added initial eASIC support
154 - Added initial ECP5 support
155
156 * GreenPAK Support
157 - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
158
159 * iCE40 Support
160 - Add "synth_ice40 -vpr"
161 - Add "synth_ice40 -nodffe"
162 - Add "synth_ice40 -json"
163 - Add Support for UltraPlus cells
164
165 * MAX10 and Cyclone IV Support
166 - Added initial version of metacommand "synth_intel".
167 - Improved write_verilog command to produce VQM netlist for Quartus Prime.
168 - Added support for MAX10 FPGA family synthesis.
169 - Added support for Cyclone IV family synthesis.
170 - Added example of implementation for DE2i-150 board.
171 - Added example of implementation for MAX10 development kit.
172 - Added LFSR example from Asic World.
173 - Added "dffinit -highlow" for mapping to Intel primitives
174
175
176 Yosys 0.6 .. Yosys 0.7
177 ----------------------
178
179 * Various
180 - Added "yosys -D" feature
181 - Added support for installed plugins in $(DATDIR)/plugins/
182 - Renamed opt_const to opt_expr
183 - Renamed opt_share to opt_merge
184 - Added "prep -flatten" and "synth -flatten"
185 - Added "prep -auto-top" and "synth -auto-top"
186 - Using "mfs" and "lutpack" in ABC lut mapping
187 - Support for abstract modules in chparam
188 - Cleanup abstract modules at end of "hierarchy -top"
189 - Added tristate buffer support to iopadmap
190 - Added opt_expr support for div/mod by power-of-two
191 - Added "select -assert-min <N> -assert-max <N>"
192 - Added "attrmvcp" pass
193 - Added "attrmap" command
194 - Added "tee +INT -INT"
195 - Added "zinit" pass
196 - Added "setparam -type"
197 - Added "shregmap" pass
198 - Added "setundef -init"
199 - Added "nlutmap -assert"
200 - Added $sop cell type and "abc -sop -I <num> -P <num>"
201 - Added "dc2" to default ABC scripts
202 - Added "deminout"
203 - Added "insbuf" command
204 - Added "prep -nomem"
205 - Added "opt_rmdff -keepdc"
206 - Added "prep -nokeepdc"
207 - Added initial version of "synth_gowin"
208 - Added "fsm_expand -full"
209 - Added support for fsm_encoding="user"
210 - Many improvements in GreenPAK4 support
211 - Added black box modules for all Xilinx 7-series lib cells
212 - Added synth_ice40 support for latches via logic loops
213 - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
214
215 * Build System
216 - Added ABCEXTERNAL and ABCURL make variables
217 - Added BINDIR, LIBDIR, and DATDIR make variables
218 - Added PKG_CONFIG make variable
219 - Added SEED make variable (for "make test")
220 - Added YOSYS_VER_STR make variable
221 - Updated min GCC requirement to GCC 4.8
222 - Updated required Bison version to Bison 3.x
223
224 * Internal APIs
225 - Added ast.h to exported headers
226 - Added ScriptPass helper class for script-like passes
227 - Added CellEdgesDatabase API
228
229 * Front-ends and Back-ends
230 - Added filename glob support to all front-ends
231 - Added avail (black-box) module params to ilang format
232 - Added $display %m support
233 - Added support for $stop Verilog system task
234 - Added support for SystemVerilog packages
235 - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
236 - Added support for "active high" and "active low" latches in read_blif and write_blif
237 - Use init value "2" for all uninitialized FFs in BLIF back-end
238 - Added "read_blif -sop"
239 - Added "write_blif -noalias"
240 - Added various write_blif options for VTR support
241 - write_json: also write module attributes.
242 - Added "write_verilog -nodec -nostr -defparam"
243 - Added "read_verilog -norestrict -assume-asserts"
244 - Added support for bus interfaces to "read_liberty -lib"
245 - Added liberty parser support for types within cell decls
246 - Added "write_verilog -renameprefix -v"
247 - Added "write_edif -nogndvcc"
248
249 * Formal Verification
250 - Support for hierarchical designs in smt2 back-end
251 - Yosys-smtbmc: Support for hierarchical VCD dumping
252 - Added $initstate cell type and vlog function
253 - Added $anyconst and $anyseq cell types and vlog functions
254 - Added printing of code loc of failed asserts to yosys-smtbmc
255 - Added memory_memx pass, "memory -memx", and "prep -memx"
256 - Added "proc_mux -ifx"
257 - Added "yosys-smtbmc -g"
258 - Deprecated "write_smt2 -regs" (by default on now)
259 - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
260 - Added support for memories to smtio.py
261 - Added "yosys-smtbmc --dump-vlogtb"
262 - Added "yosys-smtbmc --smtc --dump-smtc"
263 - Added "yosys-smtbmc --dump-all"
264 - Added assertpmux command
265 - Added "yosys-smtbmc --unroll"
266 - Added $past, $stable, $rose, $fell SVA functions
267 - Added "yosys-smtbmc --noinfo and --dummy"
268 - Added "yosys-smtbmc --noincr"
269 - Added "yosys-smtbmc --cex <filename>"
270 - Added $ff and $_FF_ cell types
271 - Added $global_clock verilog syntax support for creating $ff cells
272 - Added clk2fflogic
273
274
275 Yosys 0.5 .. Yosys 0.6
276 ----------------------
277
278 * Various
279 - Added Contributor Covenant Code of Conduct
280 - Various improvements in dict<> and pool<>
281 - Added hashlib::mfp and refactored SigMap
282 - Improved support for reals as module parameters
283 - Various improvements in SMT2 back-end
284 - Added "keep_hierarchy" attribute
285 - Verilog front-end: define `BLACKBOX in -lib mode
286 - Added API for converting internal cells to AIGs
287 - Added ENABLE_LIBYOSYS Makefile option
288 - Removed "techmap -share_map" (use "-map +/filename" instead)
289 - Switched all Python scripts to Python 3
290 - Added support for $display()/$write() and $finish() to Verilog front-end
291 - Added "yosys-smtbmc" formal verification flow
292 - Added options for clang sanitizers to Makefile
293
294 * New commands and options
295 - Added "scc -expect <N> -nofeedback"
296 - Added "proc_dlatch"
297 - Added "check"
298 - Added "select %xe %cie %coe %M %C %R"
299 - Added "sat -dump_json" (WaveJSON format)
300 - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
301 - Added "sat -stepsize" and "sat -tempinduct-step"
302 - Added "sat -show-regs -show-public -show-all"
303 - Added "write_json" (Native Yosys JSON format)
304 - Added "write_blif -attr"
305 - Added "dffinit"
306 - Added "chparam"
307 - Added "muxcover"
308 - Added "pmuxtree"
309 - Added memory_bram "make_outreg" feature
310 - Added "splice -wires"
311 - Added "dff2dffe -direct-match"
312 - Added simplemap $lut support
313 - Added "read_blif"
314 - Added "opt_share -share_all"
315 - Added "aigmap"
316 - Added "write_smt2 -mem -regs -wires"
317 - Added "memory -nordff"
318 - Added "write_smv"
319 - Added "synth -nordff -noalumacc"
320 - Added "rename -top new_name"
321 - Added "opt_const -clkinv"
322 - Added "synth -nofsm"
323 - Added "miter -assert"
324 - Added "read_verilog -noautowire"
325 - Added "read_verilog -nodpi"
326 - Added "tribuf"
327 - Added "lut2mux"
328 - Added "nlutmap"
329 - Added "qwp"
330 - Added "test_cell -noeval"
331 - Added "edgetypes"
332 - Added "equiv_struct"
333 - Added "equiv_purge"
334 - Added "equiv_mark"
335 - Added "equiv_add -try -cell"
336 - Added "singleton"
337 - Added "abc -g -luts"
338 - Added "torder"
339 - Added "write_blif -cname"
340 - Added "submod -copy"
341 - Added "dffsr2dff"
342 - Added "stat -liberty"
343
344 * Synthesis metacommands
345 - Various improvements in synth_xilinx
346 - Added synth_ice40 and synth_greenpak4
347 - Added "prep" metacommand for "synthesis lite"
348
349 * Cell library changes
350 - Added cell types to "help" system
351 - Added $meminit cell type
352 - Added $assume cell type
353 - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
354 - Added $tribuf and $_TBUF_ cell types
355 - Added read-enable to memory model
356
357 * YosysJS
358 - Various improvements in emscripten build
359 - Added alternative webworker-based JS API
360 - Added a few example applications
361
362
363 Yosys 0.4 .. Yosys 0.5
364 ----------------------
365
366 * API changes
367 - Added log_warning()
368 - Added eval_select_args() and eval_select_op()
369 - Added cell->known(), cell->input(portname), cell->output(portname)
370 - Skip blackbox modules in design->selected_modules()
371 - Replaced std::map<> and std::set<> with dict<> and pool<>
372 - New SigSpec::extend() is what used to be SigSpec::extend_u0()
373 - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
374
375 * Cell library changes
376 - Added flip-flops with enable ($dffe etc.)
377 - Added $equiv cells for equivalence checking framework
378
379 * Various
380 - Updated ABC to hg rev 61ad5f908c03
381 - Added clock domain partitioning to ABC pass
382 - Improved plugin building (see "yosys-config --build")
383 - Added ENABLE_NDEBUG Makefile flag for high-performance builds
384 - Added "yosys -d", "yosys -L" and other driver improvements
385 - Added support for multi-bit (array) cell ports to "write_edif"
386 - Now printing most output to stdout, not stderr
387 - Added "onehot" attribute (set by "fsm_map")
388 - Various performance improvements
389 - Vastly improved Xilinx flow
390 - Added "make unsintall"
391
392 * Equivalence checking
393 - Added equivalence checking commands:
394 equiv_make equiv_simple equiv_status
395 equiv_induct equiv_miter
396 equiv_add equiv_remove
397
398 * Block RAM support:
399 - Added "memory_bram" command
400 - Added BRAM support to Xilinx flow
401
402 * Other New Commands and Options
403 - Added "dff2dffe"
404 - Added "fsm -encfile"
405 - Added "dfflibmap -prepare"
406 - Added "write_blid -unbuf -undef -blackbox"
407 - Added "write_smt2" for writing SMT-LIBv2 files
408 - Added "test_cell -w -muxdiv"
409 - Added "select -read"
410
411
412 Yosys 0.3.0 .. Yosys 0.4
413 ------------------------
414
415 * Platform Support
416 - Added support for mxe-based cross-builds for win32
417 - Added sourcecode-export as VisualStudio project
418 - Added experimental EMCC (JavaScript) support
419
420 * Verilog Frontend
421 - Added -sv option for SystemVerilog (and automatic *.sv file support)
422 - Added support for real-valued constants and constant expressions
423 - Added support for non-standard "via_celltype" attribute on task/func
424 - Added support for non-standard "module mod_name(...);" syntax
425 - Added support for non-standard """ macro bodies
426 - Added support for array with more than one dimension
427 - Added support for $readmemh and $readmemb
428 - Added support for DPI functions
429
430 * Changes in internal cell library
431 - Added $shift and $shiftx cell types
432 - Added $alu, $lcu, $fa and $macc cell types
433 - Removed $bu0 and $safe_pmux cell types
434 - $mem/$memwr WR_EN input is now a per-data-bit enable signal
435 - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
436 - Renamed ports of $lut cells (from I->O to A->Y)
437 - Renamed $_INV_ to $_NOT_
438
439 * Changes for simple synthesis flows
440 - There is now a "synth" command with a recommended default script
441 - Many improvements in synthesis of arithmetic functions to gates
442 - Multipliers and adders with many operands are using carry-save adder trees
443 - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
444 - Various new high-level optimizations on RTL netlist
445 - Various improvements in FSM optimization
446 - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
447
448 * Changes in internal APIs and RTLIL
449 - Added log_id() and log_cell() helper functions
450 - Added function-like cell creation helpers
451 - Added GetSize() function (like .size() but with int)
452 - Major refactoring of RTLIL::Module and related classes
453 - Major refactoring of RTLIL::SigSpec and related classes
454 - Now RTLIL::IdString is essentially an int
455 - Added macros for code coverage counters
456 - Added some Makefile magic for pretty make logs
457 - Added "kernel/yosys.h" with all the core definitions
458 - Changed a lot of code from FILE* to c++ streams
459 - Added RTLIL::Monitor API and "trace" command
460 - Added "Yosys" C++ namespace
461
462 * Changes relevant to SAT solving
463 - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
464 - Added native ezSAT support for vector shift ops
465 - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
466
467 * New commands (or large improvements to commands)
468 - Added "synth" command with default script
469 - Added "share" (finally some real resource sharing)
470 - Added "memory_share" (reduce number of ports on memories)
471 - Added "wreduce" and "alumacc" commands
472 - Added "opt -keepdc -fine -full -fast"
473 - Added some "test_*" commands
474
475 * Various other changes
476 - Added %D and %c select operators
477 - Added support for labels in yosys scripts
478 - Added support for here-documents in yosys scripts
479 - Support "+/" prefix for files from proc_share_dir
480 - Added "autoidx" statement to ilang language
481 - Switched from "yosys-svgviewer" to "xdot"
482 - Renamed "stdcells.v" to "techmap.v"
483 - Various bug fixes and small improvements
484 - Improved welcome and bye messages
485
486
487 Yosys 0.2.0 .. Yosys 0.3.0
488 --------------------------
489
490 * Driver program and overall behavior:
491 - Added "design -push" and "design -pop"
492 - Added "tee" command for redirecting log output
493
494 * Changes in the internal cell library:
495 - Added $dlatchsr and $_DLATCHSR_???_ cell types
496
497 * Improvements in Verilog frontend:
498 - Improved support for const functions (case, always, repeat)
499 - The generate..endgenerate keywords are now optional
500 - Added support for arrays of module instances
501 - Added support for "`default_nettype" directive
502 - Added support for "`line" directive
503
504 * Other front- and back-ends:
505 - Various changes to "write_blif" options
506 - Various improvements in EDIF backend
507 - Added "vhdl2verilog" pseudo-front-end
508 - Added "verific" pseudo-front-end
509
510 * Improvements in technology mapping:
511 - Added support for recursive techmap
512 - Added CONSTMSK and CONSTVAL features to techmap
513 - Added _TECHMAP_CONNMAP_*_ feature to techmap
514 - Added _TECHMAP_REPLACE_ feature to techmap
515 - Added "connwrappers" command for wrap-extract-unwrap method
516 - Added "extract -map %<design_name>" feature
517 - Added "extract -ignore_param ..." and "extract -ignore_parameters"
518 - Added "techmap -max_iter" option
519
520 * Improvements to "eval" and "sat" framework:
521 - Now include a copy of Minisat (with build fixes applied)
522 - Switched to Minisat::SimpSolver as SAT back-end
523 - Added "sat -dump_vcd" feature
524 - Added "sat -dump_cnf" feature
525 - Added "sat -initsteps <N>" feature
526 - Added "freduce -stop <N>" feature
527 - Added "freduce -dump <prefix>" feature
528
529 * Integration with ABC:
530 - Updated ABC rev to 7600ffb9340c
531
532 * Improvements in the internal APIs:
533 - Added RTLIL::Module::add... helper methods
534 - Various build fixes for OSX (Darwin) and OpenBSD
535
536
537 Yosys 0.1.0 .. Yosys 0.2.0
538 --------------------------
539
540 * Changes to the driver program:
541 - Added "yosys -h" and "yosys -H"
542 - Added support for backslash line continuation in scripts
543 - Added support for #-comments in same line as command
544 - Added "echo" and "log" commands
545
546 * Improvements in Verilog frontend:
547 - Added support for local registers in named blocks
548 - Added support for "case" in "generate" blocks
549 - Added support for $clog2 system function
550 - Added support for basic SystemVerilog assert statements
551 - Added preprocessor support for macro arguments
552 - Added preprocessor support for `elsif statement
553 - Added "verilog_defaults" command
554 - Added read_verilog -icells option
555 - Added support for constant sizes from parameters
556 - Added "read_verilog -setattr"
557 - Added support for function returning 'integer'
558 - Added limited support for function calls in parameter values
559 - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
560
561 * Other front- and back-ends:
562 - Added BTOR backend
563 - Added Liberty frontend
564
565 * Improvements in technology mapping:
566 - The "dfflibmap" command now strongly prefers solutions with
567 no inverters in clock paths
568 - The "dfflibmap" command now prefers cells with smaller area
569 - Added support for multiple -map options to techmap
570 - Added "dfflibmap" support for //-comments in liberty files
571 - Added "memory_unpack" command to revert "memory_collect"
572 - Added standard techmap rule "techmap -share_map pmux2mux.v"
573 - Added "iopadmap -bits"
574 - Added "setundef" command
575 - Added "hilomap" command
576
577 * Changes in the internal cell library:
578 - Major rewrite of simlib.v for better compatibility with other tools
579 - Added PRIORITY parameter to $memwr cells
580 - Added TRANSPARENT parameter to $memrd cells
581 - Added RD_TRANSPARENT parameter to $mem cells
582 - Added $bu0 cell (always 0-extend, even undef MSB)
583 - Added $assert cell type
584 - Added $slice and $concat cell types
585
586 * Integration with ABC:
587 - Updated ABC to hg rev 2058c8ccea68
588 - Tighter integration of ABC build with Yosys build. The make
589 targets 'make abc' and 'make install-abc' are now obsolete.
590 - Added support for passing FFs from one clock domain through ABC
591 - Now always use BLIF as exchange format with ABC
592 - Added support for "abc -script +<command_sequence>"
593 - Improved standard ABC recipe
594 - Added support for "keep" attribute to abc command
595 - Added "abc -dff / -clk / -keepff" options
596
597 * Improvements to "eval" and "sat" framework:
598 - Added support for "0" and "~0" in right-hand side -set expressions
599 - Added "eval -set-undef" and "eval -table"
600 - Added "sat -set-init" and "sat -set-init-*" for sequential problems
601 - Added undef support to SAT solver, incl. various new "sat" options
602 - Added correct support for === and !== for "eval" and "sat"
603 - Added "sat -tempinduct" (default -seq is now non-induction sequential)
604 - Added "sat -prove-asserts"
605 - Complete rewrite of the 'freduce' command
606 - Added "miter" command
607 - Added "sat -show-inputs" and "sat -show-outputs"
608 - Added "sat -ignore_unknown_cells" (now produce an error by default)
609 - Added "sat -falsify"
610 - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
611 - Added "expose" command
612 - Added support for @<sel_name> to sat and eval signal expressions
613
614 * Changes in the 'make test' framework and auxiliary test tools:
615 - Added autotest.sh -p and -f options
616 - Replaced autotest.sh ISIM support with XSIM support
617 - Added test cases for SAT framework
618
619 * Added "abbreviated IDs":
620 - Now $<something>$foo can be abbreviated as $foo.
621 - Usually this last part is a unique id (from RTLIL::autoidx)
622 - This abbreviated IDs are now also used in "show" output
623
624 * Other changes to selection framework:
625 - Now */ is optional in */<mode>:<arg> expressions
626 - Added "select -assert-none" and "select -assert-any"
627 - Added support for matching modules by attribute (A:<expr>)
628 - Added "select -none"
629 - Added support for r:<expr> pattern for matching cell parameters
630 - Added support for !=, <, <=, >=, > for attribute and parameter matching
631 - Added support for %s for selecting sub-modules
632 - Added support for %m for expanding selections to whole modules
633 - Added support for i:*, o:* and x:* pattern for selecting module ports
634 - Added support for s:<expr> pattern for matching wire width
635 - Added support for %a operation to select wire aliases
636
637 * Various other changes to commands and options:
638 - The "ls" command now supports wildcards
639 - Added "show -pause" and "show -format dot"
640 - Added "show -color" support for cells
641 - Added "show -label" and "show -notitle"
642 - Added "dump -m" and "dump -n"
643 - Added "history" command
644 - Added "rename -hide"
645 - Added "connect" command
646 - Added "splitnets -driver"
647 - Added "opt_const -mux_undef"
648 - Added "opt_const -mux_bool"
649 - Added "opt_const -undriven"
650 - Added "opt -mux_undef -mux_bool -undriven -purge"
651 - Added "hierarchy -libdir"
652 - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
653 - Added "delete" command
654 - Added "dump -append"
655 - Added "setattr" and "setparam" commands
656 - Added "design -stash/-copy-from/-copy-to"
657 - Added "copy" command
658 - Added "splice" command
659