Merge pull request #1679 from thasti/delay-parsing
[yosys.git] / CHANGELOG
1
2 List of major changes and improvements between releases
3 =======================================================
4
5
6 Yosys 0.9 .. Yosys 0.9-dev
7 --------------------------
8
9 * Various
10 - Added "write_xaiger" backend
11 - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
12 - Added "synth_xilinx -abc9" (experimental)
13 - Added "synth_ice40 -abc9" (experimental)
14 - Added "synth -abc9" (experimental)
15 - Added "script -scriptwire"
16 - Added "synth_xilinx -nocarry"
17 - Added "synth_xilinx -nowidelut"
18 - Added "synth_ecp5 -nowidelut"
19 - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
20 - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
21 - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
22 - Renamed labels in synth_intel (e.g. bram -> map_bram)
23 - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
24 - Added automatic gzip decompression for frontends
25 - Added $_NMUX_ cell type
26 - Added automatic gzip compression (based on filename extension) for backends
27 - Improve attribute and parameter encoding in JSON to avoid ambiguities between
28 bit vectors and strings containing [01xz]*
29 - Added "clkbufmap" pass
30 - Added "extractinv" pass and "invertible_pin" attribute
31 - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
32 - Added "synth_xilinx -ise" (experimental)
33 - Added "synth_xilinx -iopad"
34 - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
35 - Improvements in pmgen: subpattern and recursive matches
36 - Added "opt_share" pass, run as part of "opt -full"
37 - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
38 - Removed "ice40_unlut"
39 - Improvements in pmgen: slices, choices, define, generate
40 - Added "xilinx_srl" for Xilinx shift register extraction
41 - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
42 - Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
43 - Added "-match-init" option to "dff2dffs" pass
44 - Added "techmap_autopurge" support to techmap
45 - Added "add -mod <modname[s]>"
46 - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
47 - Added "ice40_dsp" for Lattice iCE40 DSP packing
48 - Added "xilinx_dsp" for Xilinx DSP packing
49 - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
50 - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
51 - "synth_ice40 -dsp" to infer DSP blocks
52 - Added latch support to synth_xilinx
53 - Added support for flip-flops with synchronous reset to synth_xilinx
54 - Added support for flip-flops with reset and enable to synth_xilinx
55 - Added "check -mapped"
56 - Added checking of SystemVerilog always block types (always_comb,
57 always_latch and always_ff)
58 - Added support for SystemVerilog wildcard port connections (.*)
59 - Added "xilinx_dffopt" pass
60 - Added "scratchpad" pass
61 - Added "abc9 -dff"
62 - Added "synth_xilinx -dff"
63 - Improved support of $readmem[hb] Memory Content File inclusion
64 - Added "opt_lut_ins" pass
65
66 Yosys 0.8 .. Yosys 0.9
67 ----------------------
68
69 * Various
70 - Many bugfixes and small improvements
71 - Added support for SystemVerilog interfaces and modports
72 - Added "write_edif -attrprop"
73 - Added "opt_lut" pass
74 - Added "gate2lut.v" techmap rule
75 - Added "rename -src"
76 - Added "equiv_opt" pass
77 - Added "flowmap" LUT mapping pass
78 - Added "rename -wire" to rename cells based on the wires they drive
79 - Added "bugpoint" for creating minimised testcases
80 - Added "write_edif -gndvccy"
81 - "write_verilog" to escape Verilog keywords
82 - Fixed sign handling of real constants
83 - "write_verilog" to write initial statement for initial flop state
84 - Added pmgen pattern matcher generator
85 - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
86 - Added "setundef -params" to replace undefined cell parameters
87 - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
88 - Fixed handling of defparam when default_nettype is none
89 - Fixed "wreduce" flipflop handling
90 - Fixed FIRRTL to Verilog process instance subfield assignment
91 - Added "write_verilog -siminit"
92 - Several fixes and improvements for mem2reg memories
93 - Fixed handling of task output ports in clocked always blocks
94 - Improved handling of and-with-1 and or-with-0 in "opt_expr"
95 - Added "read_aiger" frontend
96 - Added "mutate" pass
97 - Added "hdlname" attribute
98 - Added "rename -output"
99 - Added "read_ilang -lib"
100 - Improved "proc" full_case detection and handling
101 - Added "whitebox" and "lib_whitebox" attributes
102 - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
103 - Added Python bindings and support for Python plug-ins
104 - Added "pmux2shiftx"
105 - Added log_debug framework for reduced default verbosity
106 - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
107 - Added "peepopt" peephole optimisation pass using pmgen
108 - Added approximate support for SystemVerilog "var" keyword
109 - Added parsing of "specify" blocks into $specrule and $specify[23]
110 - Added support for attributes on parameters and localparams
111 - Added support for parsing attributes on port connections
112 - Added "wreduce -keepdc"
113 - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
114 - Added Verilog wand/wor wire type support
115 - Added support for elaboration system tasks
116 - Added "muxcover -mux{4,8,16}=<cost>"
117 - Added "muxcover -dmux=<cost>"
118 - Added "muxcover -nopartial"
119 - Added "muxpack" pass
120 - Added "pmux2shiftx -norange"
121 - Added support for "~" in filename parsing
122 - Added "read_verilog -pwires" feature to turn parameters into wires
123 - Fixed sign extension of unsized constants with 'bx and 'bz MSB
124 - Fixed genvar to be a signed type
125 - Added support for attributes on case rules
126 - Added "upto" and "offset" to JSON frontend and backend
127 - Several liberty file parser improvements
128 - Fixed handling of more complex BRAM patterns
129 - Add "write_aiger -I -O -B"
130
131 * Formal Verification
132 - Added $changed support to read_verilog
133 - Added "read_verilog -noassert -noassume -assert-assumes"
134 - Added btor ops for $mul, $div, $mod and $concat
135 - Added yosys-smtbmc support for btor witnesses
136 - Added "supercover" pass
137 - Fixed $global_clock handling vs autowire
138 - Added $dffsr support to "async2sync"
139 - Added "fmcombine" pass
140 - Added memory init support in "write_btor"
141 - Added "cutpoint" pass
142 - Changed "ne" to "neq" in btor2 output
143 - Added support for SVA "final" keyword
144 - Added "fmcombine -initeq -anyeq"
145 - Added timescale and generated-by header to yosys-smtbmc vcd output
146 - Improved BTOR2 handling of undriven wires
147
148 * Verific support
149 - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
150 - Improved support for asymmetric memories
151 - Added "verific -chparam"
152 - Fixed "verific -extnets" for more complex situations
153 - Added "read -verific" and "read -noverific"
154 - Added "hierarchy -chparam"
155
156 * New back-ends
157 - Added initial Anlogic support
158 - Added initial SmartFusion2 and IGLOO2 support
159
160 * ECP5 support
161 - Added "synth_ecp5 -nowidelut"
162 - Added BRAM inference support to "synth_ecp5"
163 - Added support for transforming Diamond IO and flipflop primitives
164
165 * iCE40 support
166 - Added "ice40_unlut" pass
167 - Added "synth_ice40 -relut"
168 - Added "synth_ice40 -noabc"
169 - Added "synth_ice40 -dffe_min_ce_use"
170 - Added DSP inference support using pmgen
171 - Added support for initialising BRAM primitives from a file
172 - Added iCE40 Ultra RGB LED driver cells
173
174 * Xilinx support
175 - Use "write_edif -pvector bra" for Xilinx EDIF files
176 - Fixes for VPR place and route support with "synth_xilinx"
177 - Added more cell simulation models
178 - Added "synth_xilinx -family"
179 - Added "stat -tech xilinx" to estimate logic cell usage
180 - Added "synth_xilinx -nocarry"
181 - Added "synth_xilinx -nowidelut"
182 - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
183 - Added support for mapping RAM32X1D
184
185 Yosys 0.7 .. Yosys 0.8
186 ----------------------
187
188 * Various
189 - Many bugfixes and small improvements
190 - Strip debug symbols from installed binary
191 - Replace -ignore_redef with -[no]overwrite in front-ends
192 - Added write_verilog hex dump support, add -nohex option
193 - Added "write_verilog -decimal"
194 - Added "scc -set_attr"
195 - Added "verilog_defines" command
196 - Remember defines from one read_verilog to next
197 - Added support for hierarchical defparam
198 - Added FIRRTL back-end
199 - Improved ABC default scripts
200 - Added "design -reset-vlog"
201 - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
202 - Added Verilog $rtoi and $itor support
203 - Added "check -initdrv"
204 - Added "read_blif -wideports"
205 - Added support for SystemVerilog "++" and "--" operators
206 - Added support for SystemVerilog unique, unique0, and priority case
207 - Added "write_edif" options for edif "flavors"
208 - Added support for resetall compiler directive
209 - Added simple C beck-end (bitwise combinatorical only atm)
210 - Added $_ANDNOT_ and $_ORNOT_ cell types
211 - Added cell library aliases to "abc -g"
212 - Added "setundef -anyseq"
213 - Added "chtype" command
214 - Added "design -import"
215 - Added "write_table" command
216 - Added "read_json" command
217 - Added "sim" command
218 - Added "extract_fa" and "extract_reduce" commands
219 - Added "extract_counter" command
220 - Added "opt_demorgan" command
221 - Added support for $size and $bits SystemVerilog functions
222 - Added "blackbox" command
223 - Added "ltp" command
224 - Added support for editline as replacement for readline
225 - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
226 - Added "yosys -E" for creating Makefile dependencies files
227 - Added "synth -noshare"
228 - Added "memory_nordff"
229 - Added "setundef -undef -expose -anyconst"
230 - Added "expose -input"
231 - Added specify/specparam parser support (simply ignore them)
232 - Added "write_blif -inames -iattr"
233 - Added "hierarchy -simcheck"
234 - Added an option to statically link abc into yosys
235 - Added protobuf back-end
236 - Added BLIF parsing support for .conn and .cname
237 - Added read_verilog error checking for reg/wire/logic misuse
238 - Added "make coverage" and ENABLE_GCOV build option
239
240 * Changes in Yosys APIs
241 - Added ConstEval defaultval feature
242 - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
243 - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
244 - Added log_file_warning() and log_file_error() functions
245
246 * Formal Verification
247 - Added "write_aiger"
248 - Added "yosys-smtbmc --aig"
249 - Added "always <positive_int>" to .smtc format
250 - Added $cover cell type and support for cover properties
251 - Added $fair/$live cell type and support for liveness properties
252 - Added smtbmc support for memory vcd dumping
253 - Added "chformal" command
254 - Added "write_smt2 -stbv" and "write_smt2 -stdt"
255 - Fix equiv_simple, old behavior now available with "equiv_simple -short"
256 - Change to Yices2 as default SMT solver (it is GPL now)
257 - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
258 - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
259 - Added a brand new "write_btor" command for BTOR2
260 - Added clk2fflogic memory support and other improvements
261 - Added "async memory write" support to write_smt2
262 - Simulate clock toggling in yosys-smtbmc VCD output
263 - Added $allseq/$allconst cells for EA-solving
264 - Make -nordff the default in "prep"
265 - Added (* gclk *) attribute
266 - Added "async2sync" pass for single-clock designs with async resets
267
268 * Verific support
269 - Many improvements in Verific front-end
270 - Added proper handling of concurent SVA properties
271 - Map "const" and "rand const" to $anyseq/$anyconst
272 - Added "verific -import -flatten" and "verific -import -extnets"
273 - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
274 - Remove PSL support (because PSL has been removed in upstream Verific)
275 - Improve integration with "hierarchy" command design elaboration
276 - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
277 - Added simpilied "read" command that automatically uses verific if available
278 - Added "verific -set-<severity> <msg_id>.."
279 - Added "verific -work <libname>"
280
281 * New back-ends
282 - Added initial Coolrunner-II support
283 - Added initial eASIC support
284 - Added initial ECP5 support
285
286 * GreenPAK Support
287 - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
288
289 * iCE40 Support
290 - Add "synth_ice40 -vpr"
291 - Add "synth_ice40 -nodffe"
292 - Add "synth_ice40 -json"
293 - Add Support for UltraPlus cells
294
295 * MAX10 and Cyclone IV Support
296 - Added initial version of metacommand "synth_intel".
297 - Improved write_verilog command to produce VQM netlist for Quartus Prime.
298 - Added support for MAX10 FPGA family synthesis.
299 - Added support for Cyclone IV family synthesis.
300 - Added example of implementation for DE2i-150 board.
301 - Added example of implementation for MAX10 development kit.
302 - Added LFSR example from Asic World.
303 - Added "dffinit -highlow" for mapping to Intel primitives
304
305
306 Yosys 0.6 .. Yosys 0.7
307 ----------------------
308
309 * Various
310 - Added "yosys -D" feature
311 - Added support for installed plugins in $(DATDIR)/plugins/
312 - Renamed opt_const to opt_expr
313 - Renamed opt_share to opt_merge
314 - Added "prep -flatten" and "synth -flatten"
315 - Added "prep -auto-top" and "synth -auto-top"
316 - Using "mfs" and "lutpack" in ABC lut mapping
317 - Support for abstract modules in chparam
318 - Cleanup abstract modules at end of "hierarchy -top"
319 - Added tristate buffer support to iopadmap
320 - Added opt_expr support for div/mod by power-of-two
321 - Added "select -assert-min <N> -assert-max <N>"
322 - Added "attrmvcp" pass
323 - Added "attrmap" command
324 - Added "tee +INT -INT"
325 - Added "zinit" pass
326 - Added "setparam -type"
327 - Added "shregmap" pass
328 - Added "setundef -init"
329 - Added "nlutmap -assert"
330 - Added $sop cell type and "abc -sop -I <num> -P <num>"
331 - Added "dc2" to default ABC scripts
332 - Added "deminout"
333 - Added "insbuf" command
334 - Added "prep -nomem"
335 - Added "opt_rmdff -keepdc"
336 - Added "prep -nokeepdc"
337 - Added initial version of "synth_gowin"
338 - Added "fsm_expand -full"
339 - Added support for fsm_encoding="user"
340 - Many improvements in GreenPAK4 support
341 - Added black box modules for all Xilinx 7-series lib cells
342 - Added synth_ice40 support for latches via logic loops
343 - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
344
345 * Build System
346 - Added ABCEXTERNAL and ABCURL make variables
347 - Added BINDIR, LIBDIR, and DATDIR make variables
348 - Added PKG_CONFIG make variable
349 - Added SEED make variable (for "make test")
350 - Added YOSYS_VER_STR make variable
351 - Updated min GCC requirement to GCC 4.8
352 - Updated required Bison version to Bison 3.x
353
354 * Internal APIs
355 - Added ast.h to exported headers
356 - Added ScriptPass helper class for script-like passes
357 - Added CellEdgesDatabase API
358
359 * Front-ends and Back-ends
360 - Added filename glob support to all front-ends
361 - Added avail (black-box) module params to ilang format
362 - Added $display %m support
363 - Added support for $stop Verilog system task
364 - Added support for SystemVerilog packages
365 - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
366 - Added support for "active high" and "active low" latches in read_blif and write_blif
367 - Use init value "2" for all uninitialized FFs in BLIF back-end
368 - Added "read_blif -sop"
369 - Added "write_blif -noalias"
370 - Added various write_blif options for VTR support
371 - write_json: also write module attributes.
372 - Added "write_verilog -nodec -nostr -defparam"
373 - Added "read_verilog -norestrict -assume-asserts"
374 - Added support for bus interfaces to "read_liberty -lib"
375 - Added liberty parser support for types within cell decls
376 - Added "write_verilog -renameprefix -v"
377 - Added "write_edif -nogndvcc"
378
379 * Formal Verification
380 - Support for hierarchical designs in smt2 back-end
381 - Yosys-smtbmc: Support for hierarchical VCD dumping
382 - Added $initstate cell type and vlog function
383 - Added $anyconst and $anyseq cell types and vlog functions
384 - Added printing of code loc of failed asserts to yosys-smtbmc
385 - Added memory_memx pass, "memory -memx", and "prep -memx"
386 - Added "proc_mux -ifx"
387 - Added "yosys-smtbmc -g"
388 - Deprecated "write_smt2 -regs" (by default on now)
389 - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
390 - Added support for memories to smtio.py
391 - Added "yosys-smtbmc --dump-vlogtb"
392 - Added "yosys-smtbmc --smtc --dump-smtc"
393 - Added "yosys-smtbmc --dump-all"
394 - Added assertpmux command
395 - Added "yosys-smtbmc --unroll"
396 - Added $past, $stable, $rose, $fell SVA functions
397 - Added "yosys-smtbmc --noinfo and --dummy"
398 - Added "yosys-smtbmc --noincr"
399 - Added "yosys-smtbmc --cex <filename>"
400 - Added $ff and $_FF_ cell types
401 - Added $global_clock verilog syntax support for creating $ff cells
402 - Added clk2fflogic
403
404
405 Yosys 0.5 .. Yosys 0.6
406 ----------------------
407
408 * Various
409 - Added Contributor Covenant Code of Conduct
410 - Various improvements in dict<> and pool<>
411 - Added hashlib::mfp and refactored SigMap
412 - Improved support for reals as module parameters
413 - Various improvements in SMT2 back-end
414 - Added "keep_hierarchy" attribute
415 - Verilog front-end: define `BLACKBOX in -lib mode
416 - Added API for converting internal cells to AIGs
417 - Added ENABLE_LIBYOSYS Makefile option
418 - Removed "techmap -share_map" (use "-map +/filename" instead)
419 - Switched all Python scripts to Python 3
420 - Added support for $display()/$write() and $finish() to Verilog front-end
421 - Added "yosys-smtbmc" formal verification flow
422 - Added options for clang sanitizers to Makefile
423
424 * New commands and options
425 - Added "scc -expect <N> -nofeedback"
426 - Added "proc_dlatch"
427 - Added "check"
428 - Added "select %xe %cie %coe %M %C %R"
429 - Added "sat -dump_json" (WaveJSON format)
430 - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
431 - Added "sat -stepsize" and "sat -tempinduct-step"
432 - Added "sat -show-regs -show-public -show-all"
433 - Added "write_json" (Native Yosys JSON format)
434 - Added "write_blif -attr"
435 - Added "dffinit"
436 - Added "chparam"
437 - Added "muxcover"
438 - Added "pmuxtree"
439 - Added memory_bram "make_outreg" feature
440 - Added "splice -wires"
441 - Added "dff2dffe -direct-match"
442 - Added simplemap $lut support
443 - Added "read_blif"
444 - Added "opt_share -share_all"
445 - Added "aigmap"
446 - Added "write_smt2 -mem -regs -wires"
447 - Added "memory -nordff"
448 - Added "write_smv"
449 - Added "synth -nordff -noalumacc"
450 - Added "rename -top new_name"
451 - Added "opt_const -clkinv"
452 - Added "synth -nofsm"
453 - Added "miter -assert"
454 - Added "read_verilog -noautowire"
455 - Added "read_verilog -nodpi"
456 - Added "tribuf"
457 - Added "lut2mux"
458 - Added "nlutmap"
459 - Added "qwp"
460 - Added "test_cell -noeval"
461 - Added "edgetypes"
462 - Added "equiv_struct"
463 - Added "equiv_purge"
464 - Added "equiv_mark"
465 - Added "equiv_add -try -cell"
466 - Added "singleton"
467 - Added "abc -g -luts"
468 - Added "torder"
469 - Added "write_blif -cname"
470 - Added "submod -copy"
471 - Added "dffsr2dff"
472 - Added "stat -liberty"
473
474 * Synthesis metacommands
475 - Various improvements in synth_xilinx
476 - Added synth_ice40 and synth_greenpak4
477 - Added "prep" metacommand for "synthesis lite"
478
479 * Cell library changes
480 - Added cell types to "help" system
481 - Added $meminit cell type
482 - Added $assume cell type
483 - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
484 - Added $tribuf and $_TBUF_ cell types
485 - Added read-enable to memory model
486
487 * YosysJS
488 - Various improvements in emscripten build
489 - Added alternative webworker-based JS API
490 - Added a few example applications
491
492
493 Yosys 0.4 .. Yosys 0.5
494 ----------------------
495
496 * API changes
497 - Added log_warning()
498 - Added eval_select_args() and eval_select_op()
499 - Added cell->known(), cell->input(portname), cell->output(portname)
500 - Skip blackbox modules in design->selected_modules()
501 - Replaced std::map<> and std::set<> with dict<> and pool<>
502 - New SigSpec::extend() is what used to be SigSpec::extend_u0()
503 - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
504
505 * Cell library changes
506 - Added flip-flops with enable ($dffe etc.)
507 - Added $equiv cells for equivalence checking framework
508
509 * Various
510 - Updated ABC to hg rev 61ad5f908c03
511 - Added clock domain partitioning to ABC pass
512 - Improved plugin building (see "yosys-config --build")
513 - Added ENABLE_NDEBUG Makefile flag for high-performance builds
514 - Added "yosys -d", "yosys -L" and other driver improvements
515 - Added support for multi-bit (array) cell ports to "write_edif"
516 - Now printing most output to stdout, not stderr
517 - Added "onehot" attribute (set by "fsm_map")
518 - Various performance improvements
519 - Vastly improved Xilinx flow
520 - Added "make unsintall"
521
522 * Equivalence checking
523 - Added equivalence checking commands:
524 equiv_make equiv_simple equiv_status
525 equiv_induct equiv_miter
526 equiv_add equiv_remove
527
528 * Block RAM support:
529 - Added "memory_bram" command
530 - Added BRAM support to Xilinx flow
531
532 * Other New Commands and Options
533 - Added "dff2dffe"
534 - Added "fsm -encfile"
535 - Added "dfflibmap -prepare"
536 - Added "write_blid -unbuf -undef -blackbox"
537 - Added "write_smt2" for writing SMT-LIBv2 files
538 - Added "test_cell -w -muxdiv"
539 - Added "select -read"
540
541
542 Yosys 0.3.0 .. Yosys 0.4
543 ------------------------
544
545 * Platform Support
546 - Added support for mxe-based cross-builds for win32
547 - Added sourcecode-export as VisualStudio project
548 - Added experimental EMCC (JavaScript) support
549
550 * Verilog Frontend
551 - Added -sv option for SystemVerilog (and automatic *.sv file support)
552 - Added support for real-valued constants and constant expressions
553 - Added support for non-standard "via_celltype" attribute on task/func
554 - Added support for non-standard "module mod_name(...);" syntax
555 - Added support for non-standard """ macro bodies
556 - Added support for array with more than one dimension
557 - Added support for $readmemh and $readmemb
558 - Added support for DPI functions
559
560 * Changes in internal cell library
561 - Added $shift and $shiftx cell types
562 - Added $alu, $lcu, $fa and $macc cell types
563 - Removed $bu0 and $safe_pmux cell types
564 - $mem/$memwr WR_EN input is now a per-data-bit enable signal
565 - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
566 - Renamed ports of $lut cells (from I->O to A->Y)
567 - Renamed $_INV_ to $_NOT_
568
569 * Changes for simple synthesis flows
570 - There is now a "synth" command with a recommended default script
571 - Many improvements in synthesis of arithmetic functions to gates
572 - Multipliers and adders with many operands are using carry-save adder trees
573 - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
574 - Various new high-level optimizations on RTL netlist
575 - Various improvements in FSM optimization
576 - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
577
578 * Changes in internal APIs and RTLIL
579 - Added log_id() and log_cell() helper functions
580 - Added function-like cell creation helpers
581 - Added GetSize() function (like .size() but with int)
582 - Major refactoring of RTLIL::Module and related classes
583 - Major refactoring of RTLIL::SigSpec and related classes
584 - Now RTLIL::IdString is essentially an int
585 - Added macros for code coverage counters
586 - Added some Makefile magic for pretty make logs
587 - Added "kernel/yosys.h" with all the core definitions
588 - Changed a lot of code from FILE* to c++ streams
589 - Added RTLIL::Monitor API and "trace" command
590 - Added "Yosys" C++ namespace
591
592 * Changes relevant to SAT solving
593 - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
594 - Added native ezSAT support for vector shift ops
595 - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
596
597 * New commands (or large improvements to commands)
598 - Added "synth" command with default script
599 - Added "share" (finally some real resource sharing)
600 - Added "memory_share" (reduce number of ports on memories)
601 - Added "wreduce" and "alumacc" commands
602 - Added "opt -keepdc -fine -full -fast"
603 - Added some "test_*" commands
604
605 * Various other changes
606 - Added %D and %c select operators
607 - Added support for labels in yosys scripts
608 - Added support for here-documents in yosys scripts
609 - Support "+/" prefix for files from proc_share_dir
610 - Added "autoidx" statement to ilang language
611 - Switched from "yosys-svgviewer" to "xdot"
612 - Renamed "stdcells.v" to "techmap.v"
613 - Various bug fixes and small improvements
614 - Improved welcome and bye messages
615
616
617 Yosys 0.2.0 .. Yosys 0.3.0
618 --------------------------
619
620 * Driver program and overall behavior:
621 - Added "design -push" and "design -pop"
622 - Added "tee" command for redirecting log output
623
624 * Changes in the internal cell library:
625 - Added $dlatchsr and $_DLATCHSR_???_ cell types
626
627 * Improvements in Verilog frontend:
628 - Improved support for const functions (case, always, repeat)
629 - The generate..endgenerate keywords are now optional
630 - Added support for arrays of module instances
631 - Added support for "`default_nettype" directive
632 - Added support for "`line" directive
633
634 * Other front- and back-ends:
635 - Various changes to "write_blif" options
636 - Various improvements in EDIF backend
637 - Added "vhdl2verilog" pseudo-front-end
638 - Added "verific" pseudo-front-end
639
640 * Improvements in technology mapping:
641 - Added support for recursive techmap
642 - Added CONSTMSK and CONSTVAL features to techmap
643 - Added _TECHMAP_CONNMAP_*_ feature to techmap
644 - Added _TECHMAP_REPLACE_ feature to techmap
645 - Added "connwrappers" command for wrap-extract-unwrap method
646 - Added "extract -map %<design_name>" feature
647 - Added "extract -ignore_param ..." and "extract -ignore_parameters"
648 - Added "techmap -max_iter" option
649
650 * Improvements to "eval" and "sat" framework:
651 - Now include a copy of Minisat (with build fixes applied)
652 - Switched to Minisat::SimpSolver as SAT back-end
653 - Added "sat -dump_vcd" feature
654 - Added "sat -dump_cnf" feature
655 - Added "sat -initsteps <N>" feature
656 - Added "freduce -stop <N>" feature
657 - Added "freduce -dump <prefix>" feature
658
659 * Integration with ABC:
660 - Updated ABC rev to 7600ffb9340c
661
662 * Improvements in the internal APIs:
663 - Added RTLIL::Module::add... helper methods
664 - Various build fixes for OSX (Darwin) and OpenBSD
665
666
667 Yosys 0.1.0 .. Yosys 0.2.0
668 --------------------------
669
670 * Changes to the driver program:
671 - Added "yosys -h" and "yosys -H"
672 - Added support for backslash line continuation in scripts
673 - Added support for #-comments in same line as command
674 - Added "echo" and "log" commands
675
676 * Improvements in Verilog frontend:
677 - Added support for local registers in named blocks
678 - Added support for "case" in "generate" blocks
679 - Added support for $clog2 system function
680 - Added support for basic SystemVerilog assert statements
681 - Added preprocessor support for macro arguments
682 - Added preprocessor support for `elsif statement
683 - Added "verilog_defaults" command
684 - Added read_verilog -icells option
685 - Added support for constant sizes from parameters
686 - Added "read_verilog -setattr"
687 - Added support for function returning 'integer'
688 - Added limited support for function calls in parameter values
689 - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
690
691 * Other front- and back-ends:
692 - Added BTOR backend
693 - Added Liberty frontend
694
695 * Improvements in technology mapping:
696 - The "dfflibmap" command now strongly prefers solutions with
697 no inverters in clock paths
698 - The "dfflibmap" command now prefers cells with smaller area
699 - Added support for multiple -map options to techmap
700 - Added "dfflibmap" support for //-comments in liberty files
701 - Added "memory_unpack" command to revert "memory_collect"
702 - Added standard techmap rule "techmap -share_map pmux2mux.v"
703 - Added "iopadmap -bits"
704 - Added "setundef" command
705 - Added "hilomap" command
706
707 * Changes in the internal cell library:
708 - Major rewrite of simlib.v for better compatibility with other tools
709 - Added PRIORITY parameter to $memwr cells
710 - Added TRANSPARENT parameter to $memrd cells
711 - Added RD_TRANSPARENT parameter to $mem cells
712 - Added $bu0 cell (always 0-extend, even undef MSB)
713 - Added $assert cell type
714 - Added $slice and $concat cell types
715
716 * Integration with ABC:
717 - Updated ABC to hg rev 2058c8ccea68
718 - Tighter integration of ABC build with Yosys build. The make
719 targets 'make abc' and 'make install-abc' are now obsolete.
720 - Added support for passing FFs from one clock domain through ABC
721 - Now always use BLIF as exchange format with ABC
722 - Added support for "abc -script +<command_sequence>"
723 - Improved standard ABC recipe
724 - Added support for "keep" attribute to abc command
725 - Added "abc -dff / -clk / -keepff" options
726
727 * Improvements to "eval" and "sat" framework:
728 - Added support for "0" and "~0" in right-hand side -set expressions
729 - Added "eval -set-undef" and "eval -table"
730 - Added "sat -set-init" and "sat -set-init-*" for sequential problems
731 - Added undef support to SAT solver, incl. various new "sat" options
732 - Added correct support for === and !== for "eval" and "sat"
733 - Added "sat -tempinduct" (default -seq is now non-induction sequential)
734 - Added "sat -prove-asserts"
735 - Complete rewrite of the 'freduce' command
736 - Added "miter" command
737 - Added "sat -show-inputs" and "sat -show-outputs"
738 - Added "sat -ignore_unknown_cells" (now produce an error by default)
739 - Added "sat -falsify"
740 - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
741 - Added "expose" command
742 - Added support for @<sel_name> to sat and eval signal expressions
743
744 * Changes in the 'make test' framework and auxiliary test tools:
745 - Added autotest.sh -p and -f options
746 - Replaced autotest.sh ISIM support with XSIM support
747 - Added test cases for SAT framework
748
749 * Added "abbreviated IDs":
750 - Now $<something>$foo can be abbreviated as $foo.
751 - Usually this last part is a unique id (from RTLIL::autoidx)
752 - This abbreviated IDs are now also used in "show" output
753
754 * Other changes to selection framework:
755 - Now */ is optional in */<mode>:<arg> expressions
756 - Added "select -assert-none" and "select -assert-any"
757 - Added support for matching modules by attribute (A:<expr>)
758 - Added "select -none"
759 - Added support for r:<expr> pattern for matching cell parameters
760 - Added support for !=, <, <=, >=, > for attribute and parameter matching
761 - Added support for %s for selecting sub-modules
762 - Added support for %m for expanding selections to whole modules
763 - Added support for i:*, o:* and x:* pattern for selecting module ports
764 - Added support for s:<expr> pattern for matching wire width
765 - Added support for %a operation to select wire aliases
766
767 * Various other changes to commands and options:
768 - The "ls" command now supports wildcards
769 - Added "show -pause" and "show -format dot"
770 - Added "show -color" support for cells
771 - Added "show -label" and "show -notitle"
772 - Added "dump -m" and "dump -n"
773 - Added "history" command
774 - Added "rename -hide"
775 - Added "connect" command
776 - Added "splitnets -driver"
777 - Added "opt_const -mux_undef"
778 - Added "opt_const -mux_bool"
779 - Added "opt_const -undriven"
780 - Added "opt -mux_undef -mux_bool -undriven -purge"
781 - Added "hierarchy -libdir"
782 - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
783 - Added "delete" command
784 - Added "dump -append"
785 - Added "setattr" and "setparam" commands
786 - Added "design -stash/-copy-from/-copy-to"
787 - Added "copy" command
788 - Added "splice" command
789