CHANGELOG

   1
   2 List of major changes and improvements between releases
   3 =======================================================
   4
   5
   6 Yosys 0.5 .. Yosys 0.6
   7 ----------------------
   8
   9  * Various
  10      - Added Contributor Covenant Code of Conduct
  11      - Various improvements in dict<> and pool<>
  12      - Added hashlib::mfp and refactored SigMap
  13      - Improved support for reals as module parameters
  14      - Various improvements in SMT2 back-end
  15      - Added "keep_hierarchy" attribute
  16      - Verilog front-end: define `BLACKBOX in -lib mode
  17      - Added API for converting internal cells to AIGs
  18      - Added ENABLE_LIBYOSYS Makefile option
  19      - Removed "techmap -share_map" (use "-map +/filename" instead)
  20      - Switched all Python scripts to Python 3
  21      - Added support for $display()/$write() and $finish() to Verilog front-end
  22      - Added "yosys-smtbmc" formal verification flow
  23      - Added options for clang sanitizers to Makefile
  24
  25  * New commands and options
  26      - Added "scc -expect <N> -nofeedback"
  27      - Added "proc_dlatch"
  28      - Added "check"
  29      - Added "select %xe %cie %coe %M %C %R"
  30      - Added "sat -dump_json" (WaveJSON format)
  31      - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
  32      - Added "sat -stepsize" and "sat -tempinduct-step"
  33      - Added "sat -show-regs -show-public -show-all"
  34      - Added "write_json" (Native Yosys JSON format)
  35      - Added "write_blif -attr"
  36      - Added "dffinit"
  37      - Added "chparam"
  38      - Added "muxcover"
  39      - Added "pmuxtree"
  40      - Added memory_bram "make_outreg" feature
  41      - Added "splice -wires"
  42      - Added "dff2dffe -direct-match"
  43      - Added simplemap $lut support
  44      - Added "read_blif"
  45      - Added "opt_share -share_all"
  46      - Added "aigmap"
  47      - Added "write_smt2 -mem -regs -wires"
  48      - Added "memory -nordff"
  49      - Added "write_smv"
  50      - Added "synth -nordff -noalumacc"
  51      - Added "rename -top new_name"
  52      - Added "opt_const -clkinv"
  53      - Added "synth -nofsm"
  54      - Added "miter -assert"
  55      - Added "read_verilog -noautowire"
  56      - Added "read_verilog -nodpi"
  57      - Added "tribuf"
  58      - Added "lut2mux"
  59      - Added "nlutmap"
  60      - Added "qwp"
  61      - Added "test_cell -noeval"
  62      - Added "edgetypes"
  63      - Added "equiv_struct"
  64      - Added "equiv_purge"
  65      - Added "equiv_mark"
  66      - Added "equiv_add -try -cell"
  67      - Added "singleton"
  68      - Added "abc -g -luts"
  69      - Added "torder"
  70      - Added "write_blif -cname"
  71      - Added "submod -copy"
  72      - Added "dffsr2dff"
  73      - Added "stat -liberty"
  74
  75  * Synthesis metacommands
  76      - Various improvements in synth_xilinx
  77      - Added synth_ice40 and synth_greenpak4
  78      - Added "prep" metacommand for "synthesis lite"
  79
  80  * Cell library changes
  81      - Added cell types to "help" system
  82      - Added $meminit cell type
  83      - Added $assume cell type
  84      - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
  85      - Added $tribuf and $_TBUF_ cell types
  86      - Added read-enable to memory model
  87
  88  * YosysJS
  89      - Various improvements in emscripten build
  90      - Added alternative webworker-based JS API
  91      - Added a few example applications
  92
  93
  94 Yosys 0.4 .. Yosys 0.5
  95 ----------------------
  96
  97  * API changes
  98      - Added log_warning()
  99      - Added eval_select_args() and eval_select_op()
 100      - Added cell->known(), cell->input(portname), cell->output(portname)
 101      - Skip blackbox modules in design->selected_modules()
 102      - Replaced std::map<> and std::set<> with dict<> and pool<>
 103      - New SigSpec::extend() is what used to be SigSpec::extend_u0()
 104      - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
 105
 106  * Cell library changes
 107      - Added flip-flops with enable ($dffe etc.)
 108      - Added $equiv cells for equivalence checking framework
 109
 110  * Various
 111      - Updated ABC to hg rev 61ad5f908c03
 112      - Added clock domain partitioning to ABC pass
 113      - Improved plugin building (see "yosys-config --build")
 114      - Added ENABLE_NDEBUG Makefile flag for high-performance builds
 115      - Added "yosys -d", "yosys -L" and other driver improvements
 116      - Added support for multi-bit (array) cell ports to "write_edif"
 117      - Now printing most output to stdout, not stderr
 118      - Added "onehot" attribute (set by "fsm_map")
 119      - Various performance improvements
 120      - Vastly improved Xilinx flow
 121      - Added "make unsintall"
 122
 123  * Equivalence checking
 124      - Added equivalence checking commands:
 125          equiv_make equiv_simple equiv_status
 126          equiv_induct equiv_miter
 127          equiv_add equiv_remove
 128
 129  * Block RAM support:
 130      - Added "memory_bram" command
 131      - Added BRAM support to Xilinx flow
 132
 133  * Other New Commands and Options
 134      - Added "dff2dffe"
 135      - Added "fsm -encfile"
 136      - Added "dfflibmap -prepare"
 137      - Added "write_blid -unbuf -undef -blackbox"
 138      - Added "write_smt2" for writing SMT-LIBv2 files
 139      - Added "test_cell -w -muxdiv"
 140      - Added "select -read"
 141
 142
 143 Yosys 0.3.0 .. Yosys 0.4
 144 ------------------------
 145
 146  * Platform Support
 147      - Added support for mxe-based cross-builds for win32
 148      - Added sourcecode-export as VisualStudio project
 149      - Added experimental EMCC (JavaScript) support
 150
 151  * Verilog Frontend
 152      - Added -sv option for SystemVerilog (and automatic *.sv file support)
 153      - Added support for real-valued constants and constant expressions
 154      - Added support for non-standard "via_celltype" attribute on task/func
 155      - Added support for non-standard "module mod_name(...);" syntax
 156      - Added support for non-standard """ macro bodies
 157      - Added support for array with more than one dimension
 158      - Added support for $readmemh and $readmemb
 159      - Added support for DPI functions
 160
 161  * Changes in internal cell library
 162      - Added $shift and $shiftx cell types
 163      - Added $alu, $lcu, $fa and $macc cell types
 164      - Removed $bu0 and $safe_pmux cell types
 165      - $mem/$memwr WR_EN input is now a per-data-bit enable signal
 166      - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
 167      - Renamed ports of $lut cells (from I->O to A->Y)
 168      - Renamed $_INV_ to $_NOT_
 169
 170  * Changes for simple synthesis flows
 171      - There is now a "synth" command with a recommended default script
 172      - Many improvements in synthesis of arithmetic functions to gates
 173          - Multipliers and adders with many operands are using carry-save adder trees
 174          - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
 175      - Various new high-level optimizations on RTL netlist
 176      - Various improvements in FSM optimization
 177      - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
 178
 179  * Changes in internal APIs and RTLIL
 180      - Added log_id() and log_cell() helper functions
 181      - Added function-like cell creation helpers
 182      - Added GetSize() function (like .size() but with int)
 183      - Major refactoring of RTLIL::Module and related classes
 184      - Major refactoring of RTLIL::SigSpec and related classes
 185      - Now RTLIL::IdString is essentially an int
 186      - Added macros for code coverage counters
 187      - Added some Makefile magic for pretty make logs
 188      - Added "kernel/yosys.h" with all the core definitions
 189      - Changed a lot of code from FILE* to c++ streams
 190      - Added RTLIL::Monitor API and "trace" command
 191      - Added "Yosys" C++ namespace
 192
 193  * Changes relevant to SAT solving
 194      - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
 195      - Added native ezSAT support for vector shift ops
 196      - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
 197
 198  * New commands (or large improvements to commands)
 199      - Added "synth" command with default script
 200      - Added "share" (finally some real resource sharing)
 201      - Added "memory_share" (reduce number of ports on memories)
 202      - Added "wreduce" and "alumacc" commands
 203      - Added "opt -keepdc -fine -full -fast"
 204      - Added some "test_*" commands
 205
 206  * Various other changes
 207      - Added %D and %c select operators
 208      - Added support for labels in yosys scripts
 209      - Added support for here-documents in yosys scripts
 210      - Support "+/" prefix for files from proc_share_dir
 211      - Added "autoidx" statement to ilang language
 212      - Switched from "yosys-svgviewer" to "xdot"
 213      - Renamed "stdcells.v" to "techmap.v"
 214      - Various bug fixes and small improvements
 215      - Improved welcome and bye messages
 216
 217
 218 Yosys 0.2.0 .. Yosys 0.3.0
 219 --------------------------
 220
 221  * Driver program and overall behavior:
 222      - Added "design -push" and "design -pop"
 223      - Added "tee" command for redirecting log output
 224
 225  * Changes in the internal cell library:
 226      - Added $dlatchsr and $_DLATCHSR_???_ cell types
 227
 228  * Improvements in Verilog frontend:
 229      - Improved support for const functions (case, always, repeat)
 230      - The generate..endgenerate keywords are now optional
 231      - Added support for arrays of module instances
 232      - Added support for "`default_nettype" directive
 233      - Added support for "`line" directive
 234
 235  * Other front- and back-ends:
 236      - Various changes to "write_blif" options
 237      - Various improvements in EDIF backend
 238      - Added "vhdl2verilog" pseudo-front-end
 239      - Added "verific" pseudo-front-end
 240
 241  * Improvements in technology mapping:
 242      - Added support for recursive techmap
 243      - Added CONSTMSK and CONSTVAL features to techmap
 244      - Added _TECHMAP_CONNMAP_*_ feature to techmap
 245      - Added _TECHMAP_REPLACE_ feature to techmap
 246      - Added "connwrappers" command for wrap-extract-unwrap method
 247      - Added "extract -map %<design_name>" feature
 248      - Added "extract -ignore_param ..." and "extract -ignore_parameters"
 249      - Added "techmap -max_iter" option
 250
 251  * Improvements to "eval" and "sat" framework:
 252      - Now include a copy of Minisat (with build fixes applied)
 253      - Switched to Minisat::SimpSolver as SAT back-end
 254      - Added "sat -dump_vcd" feature
 255      - Added "sat -dump_cnf" feature
 256      - Added "sat -initsteps <N>" feature
 257      - Added "freduce -stop <N>" feature
 258      - Added "freduce -dump <prefix>" feature
 259
 260  * Integration with ABC:
 261      - Updated ABC rev to 7600ffb9340c
 262
 263  * Improvements in the internal APIs:
 264      - Added RTLIL::Module::add... helper methods
 265      - Various build fixes for OSX (Darwin) and OpenBSD
 266
 267
 268 Yosys 0.1.0 .. Yosys 0.2.0
 269 --------------------------
 270
 271  * Changes to the driver program:
 272      - Added "yosys -h" and "yosys -H"
 273      - Added support for backslash line continuation in scripts
 274      - Added support for #-comments in same line as command
 275      - Added "echo" and "log" commands
 276
 277  * Improvements in Verilog frontend:
 278      - Added support for local registers in named blocks
 279      - Added support for "case" in "generate" blocks
 280      - Added support for $clog2 system function
 281      - Added support for basic SystemVerilog assert statements
 282      - Added preprocessor support for macro arguments
 283      - Added preprocessor support for `elsif statement
 284      - Added "verilog_defaults" command
 285      - Added read_verilog -icells option
 286      - Added support for constant sizes from parameters
 287      - Added "read_verilog -setattr"
 288      - Added support for function returning 'integer'
 289      - Added limited support for function calls in parameter values
 290      - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
 291
 292  * Other front- and back-ends:
 293      - Added BTOR backend
 294      - Added Liberty frontend
 295
 296  * Improvements in technology mapping:
 297      - The "dfflibmap" command now strongly prefers solutions with
 298            no inverters in clock paths
 299      - The "dfflibmap" command now prefers cells with smaller area
 300      - Added support for multiple -map options to techmap
 301      - Added "dfflibmap" support for //-comments in liberty files
 302      - Added "memory_unpack" command to revert "memory_collect"
 303      - Added standard techmap rule "techmap -share_map pmux2mux.v"
 304      - Added "iopadmap -bits"
 305      - Added "setundef" command
 306      - Added "hilomap" command
 307
 308  * Changes in the internal cell library:
 309      - Major rewrite of simlib.v for better compatibility with other tools
 310      - Added PRIORITY parameter to $memwr cells
 311      - Added TRANSPARENT parameter to $memrd cells
 312      - Added RD_TRANSPARENT parameter to $mem cells
 313      - Added $bu0 cell (always 0-extend, even undef MSB)
 314      - Added $assert cell type
 315      - Added $slice and $concat cell types
 316
 317  * Integration with ABC:
 318      - Updated ABC to hg rev 2058c8ccea68
 319      - Tighter integration of ABC build with Yosys build. The make
 320            targets 'make abc' and 'make install-abc' are now obsolete.
 321      - Added support for passing FFs from one clock domain through ABC
 322      - Now always use BLIF as exchange format with ABC
 323      - Added support for "abc -script +<command_sequence>"
 324      - Improved standard ABC recipe
 325      - Added support for "keep" attribute to abc command
 326      - Added "abc -dff / -clk / -keepff" options
 327
 328  * Improvements to "eval" and "sat" framework:
 329      - Added support for "0" and "~0" in right-hand side -set expressions
 330      - Added "eval -set-undef" and "eval -table"
 331      - Added "sat -set-init" and "sat -set-init-*" for sequential problems
 332      - Added undef support to SAT solver, incl. various new "sat" options
 333      - Added correct support for === and !== for "eval" and "sat"
 334      - Added "sat -tempinduct" (default -seq is now non-induction sequential)
 335      - Added "sat -prove-asserts"
 336      - Complete rewrite of the 'freduce' command
 337      - Added "miter" command
 338      - Added "sat -show-inputs" and "sat -show-outputs"
 339      - Added "sat -ignore_unknown_cells" (now produce an error by default)
 340      - Added "sat -falsify"
 341      - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
 342      - Added "expose" command
 343      - Added support for @<sel_name> to sat and eval signal expressions
 344
 345  * Changes in the 'make test' framework and auxiliary test tools:
 346      - Added autotest.sh -p and -f options
 347      - Replaced autotest.sh ISIM support with XSIM support
 348      - Added test cases for SAT framework
 349
 350  * Added "abbreviated IDs":
 351      - Now $<something>$foo can be abbreviated as $foo.
 352      - Usually this last part is a unique id (from RTLIL::autoidx)
 353      - This abbreviated IDs are now also used in "show" output
 354
 355  * Other changes to selection framework:
 356      - Now */ is optional in */<mode>:<arg> expressions
 357      - Added "select -assert-none" and "select -assert-any"
 358      - Added support for matching modules by attribute (A:<expr>)
 359      - Added "select -none"
 360      - Added support for r:<expr> pattern for matching cell parameters
 361      - Added support for !=, <, <=, >=, > for attribute and parameter matching
 362      - Added support for %s for selecting sub-modules
 363      - Added support for %m for expanding selections to whole modules
 364      - Added support for i:*, o:* and x:* pattern for selecting module ports
 365      - Added support for s:<expr> pattern for matching wire width
 366      - Added support for %a operation to select wire aliases
 367
 368  * Various other changes to commands and options:
 369      - The "ls" command now supports wildcards
 370      - Added "show -pause" and "show -format dot"
 371      - Added "show -color" support for cells
 372      - Added "show -label" and "show -notitle"
 373      - Added "dump -m" and "dump -n"
 374      - Added "history" command
 375      - Added "rename -hide"
 376      - Added "connect" command
 377      - Added "splitnets -driver"
 378      - Added "opt_const -mux_undef"
 379      - Added "opt_const -mux_bool"
 380      - Added "opt_const -undriven"
 381      - Added "opt -mux_undef -mux_bool -undriven -purge"
 382      - Added "hierarchy -libdir"
 383      - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
 384      - Added "delete" command
 385      - Added "dump -append"
 386      - Added "setattr" and "setparam" commands
 387      - Added "design -stash/-copy-from/-copy-to"
 388      - Added "copy" command
 389      - Added "splice" command
 390