CHANGES

   1 [> 2020.XX, planned for July 2020
   2 ---------------------------------
   3
   4         [> Issues resolved
   5         ------------------
   6         - Fix flush_cpu_icache on VexRiscv.
   7         - Fix `.data` section placed in rom (#566)
   8
   9         [> Added Features
  10         ------------------
  11         - Properly integrate Minerva CPU.
  12         - Add nMigen dependency.
  13         - Pluggable CPUs.
  14         - BIOS history, autocomplete.
  15         - Improve boards's programmers.
  16         - Add Microwatt CPU support (with GHDL-Yosys-plugin support for FOSS toolchains).
  17         - Speedup Memtest using an LFSR.
  18         - Add LedChaser on boards.
  19         - Improve WishboneBridge.
  20         - Improve Diamond constraints.
  21         - Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
  22         - Add CV32E40P CPU support (ex RI5CY).
  23         - JTAG UART with uart_name=jtag_uart (validated on Spartan6, 7-Series, Ultrascale(+)).
  24         - Add Symbiflow experimental support on Arty.
  25         - Add SDCard boot from FAT/exFAT filesystems with FatFs.
  26         - Simplify boot with boot.json configuration file.
  27         - Revert to a single crt0 (avoid ctr/xip variants).
  28
  29         [> API changes/Deprecation
  30         --------------------------
  31         - Add --build --load arguments to targets.
  32         - Deprecate soc.interconnect.wishbone.UpConverter (will be rewritten if useful).
  33         - Deprecate soc.interconnect.wishbone.CSRBank (Does not seem to be used by anyone).
  34         - Move soc.interconnect.wishbone2csr.WB2CSR to soc.interconnect.wishbone.Wishbone2CSR.
  35         - Move soc.interconnect.wishbonebridge.WishboneStreamingBridge to soc.cores.uart.Stream2Wishbone.
  36         - Rename --gateware-toolchain target parameter to --toolchain.
  37
  38 [> 2020.04, released April 28th, 2020
  39 -------------------------------------
  40
  41         [> Description
  42         --------------
  43         First release of LiteX and the ecosystem of cores!
  44
  45         LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create
  46         Cores/SoCs (with or without CPU).
  47
  48         The common components of a SoC are provided directly:
  49         - Buses and Streams (Wishbone, AXI, Avalon-ST)
  50         - Interconnect
  51         - Common cores (RAM, ROM, Timer, UART, etc...)
  52         - CPU wrappers/integration
  53         - etc...
  54         And SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM,
  55         PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX.
  56
  57         It also provides build backends for open-source and vendors toolchains.
  58
  59         [> Issues resolved
  60         ------------------
  61         - NA
  62
  63         [> Added Features
  64         ------------------
  65         - NA
  66
  67         [> API changes/Deprecation
  68         --------------------------
  69         - https://github.com/enjoy-digital/litex/pull/399: Converting LiteX to use Python modules.