CHECKLISTS

   1
   2 This file contains checklists for various tasks.
   3
   4
   5 Table of contents
   6 =================
   7
   8 1. Checklist for creating Yosys releases
   9 2. Checklist for adding internal cell types
  10
  11
  12 1. Checklist for creating Yosys releases
  13 ========================================
  14
  15
  16 Update the CHANGELOG file:
  17
  18         cd ~yosys
  19         gitk &
  20         vi CHANGELOG
  21
  22
  23 Run all tests with "make config-{clang-debug,gcc-debug,gcc-4.6,release}":
  24
  25         cd ~yosys
  26         make clean
  27         make test vloghtb
  28         make install
  29
  30         cd ~yosys-bigsim
  31         make clean
  32         make full
  33
  34         cd ~vloghammer
  35         make purge
  36         make gen_issues gen_samples
  37         make SYN_LIST="yosys" SIM_LIST="icarus yosim verilator" FULL=1 world
  38         chromium-browser report.html
  39
  40
  41 Then with default config setting:
  42
  43         cd ~yosys
  44         ./yosys -p 'proc; show' tests/simple/fiedler-cooley.v
  45         ./yosys -p 'proc; opt; show' tests/simple/fiedler-cooley.v
  46
  47         cd ~yosys
  48         make manual
  49         - sanity check the figures in the appnotes and presentation
  50             - if there are any odd things -> investigate
  51             - make cosmetic changes to the .tex files if necessary
  52
  53
  54 Also with default config setting:
  55
  56         cd ~yosys/techlibs/cmos
  57         bash testbench.sh
  58
  59         cd ~yosys/techlibs/xilinx/example_sim_counter
  60         bash run_sim.sh
  61
  62         cd ~yosys/techlibs/xilinx/example_mojo_counter
  63         bash example.sh
  64
  65
  66 Finally if a current verific library is available:
  67
  68         cd ~yosys
  69         cat frontends/verific/build_amd64.txt
  70         - follow instructions
  71
  72         cd frontends/verific
  73         ../../yosys test_navre.ys
  74
  75
  76 Release candiate:
  77
  78         - create branch yosys-x.y.z-rc and push to github
  79         - contact the usual suspects per mail and ask them to test
  80         - post on the reddit and ask people to test
  81         - commit KISS fixes to the -rc branch if necessary
  82
  83
  84 Release:
  85
  86         - set YOSYS_VER to x.y.z in Makefile
  87         - update version string in CHANGELOG
  88         git commit -am "Yosys x.y.z"
  89
  90         - push tag to github
  91         - post changelog on github
  92         - post short release note on reddit
  93         - delete -rc branch from github
  94
  95
  96 Updating the website:
  97
  98         cd ~yosys
  99         make manual
 100         make install
 101
 102         - update pdf files on the website
 103
 104         cd ~yosys-web
 105         make update_cmd
 106         make update_show
 107         git commit -am update
 108         make push
 109
 110
 111 In master branch:
 112
 113         git merge {release-tag}
 114         - set version to x.y.z+ in Makefile
 115         - add section "Yosys x.y.z .. x.y.z+" to CHANGELOG
 116         git commit --amend -am "Yosys x.y.z+"
 117
 118
 119 2. Checklist for adding internal cell types
 120 ===========================================
 121
 122 Things to do right away:
 123
 124         - Add to kernel/celltypes.h (incl. eval() handling for non-mem cells)
 125         - Add to InternalCellChecker::check() in kernel/rtlil.cc
 126         - Add to techlibs/common/simlib.v
 127         - Add to techlibs/common/techmap.v
 128
 129 Things to do after finalizing the cell interface:
 130
 131         - Add support to kernel/satgen.h for the new cell type
 132         - Add to manual/CHAPTER_CellLib.tex (or just add a fixme to the bottom)
 133         - Maybe add support to the verilog backend for dumping such cells as expression
 134