2 This file contains checklists for various tasks.
8 1. Checklist for creating Yosys releases
9 2. Checklist for adding internal cell types
12 1. Checklist for creating Yosys releases
13 ========================================
16 Update the CHANGELOG file:
23 Run all tests with "make config-{clang-debug,gcc-debug,gcc-4.6,release}":
36 make gen_issues gen_samples
37 make SYN_LIST="yosys" SIM_LIST="icarus yosim verilator" FULL=1 world
38 chromium-browser report.html
41 Then with default config setting:
44 ./yosys -p 'proc; show' tests/simple/fiedler-cooley.v
45 ./yosys -p 'proc; opt; show' tests/simple/fiedler-cooley.v
49 - sanity check the figures in the appnotes and presentation
50 - if there are any odd things -> investigate
51 - make cosmetic changes to the .tex files if necessary
54 Also with default config setting:
56 cd ~yosys/techlibs/cmos
59 cd ~yosys/techlibs/xilinx/example_sim_counter
62 cd ~yosys/techlibs/xilinx/example_mojo_counter
66 Finally if a current verific library is available:
69 cat frontends/verific/build_amd64.txt
73 ../../yosys test_navre.ys
78 - create branch yosys-x.y.z-rc and push to github
79 - contact the usual suspects per mail and ask them to test
80 - post on the reddit and ask people to test
81 - commit KISS fixes to the -rc branch if necessary
86 - set YOSYS_VER to x.y.z in Makefile
87 - update version string in CHANGELOG
88 git commit -am "Yosys x.y.z"
91 - post changelog on github
92 - post short release note on reddit
93 - delete -rc branch from github
102 - update pdf files on the website
107 git commit -am update
113 git merge {release-tag}
114 - set version to x.y.z+ in Makefile
115 - add section "Yosys x.y.z .. x.y.z+" to CHANGELOG
116 git commit --amend -am "Yosys x.y.z+"
119 2. Checklist for adding internal cell types
120 ===========================================
122 Things to do right away:
124 - Add to kernel/celltypes.h (incl. eval() handling for non-mem cells)
125 - Add to InternalCellChecker::check() in kernel/rtlil.cc
126 - Add to techlibs/common/simlib.v
127 - Add to techlibs/common/techmap.v
129 Things to do after finalizing the cell interface:
131 - Add support to kernel/satgen.h for the new cell type
132 - Add to manual/CHAPTER_CellLib.tex (or just add a fixme to the bottom)
133 - Maybe add support to the verilog backend for dumping such cells as expression