Merge pull request #2510 from YosysHQ/whitequark/CODEOWNERS-verilog-ast
[yosys.git] / CODEOWNERS
1 ## CODE NOTIFICATIONS
2 # Register yourself here to be notified about modifications
3 # for any files you have an interest in/know your way around.
4
5 # Each line is a file pattern followed by one or more users.
6 # Both github usernames and email addresses are supported.
7 # Order is important; the last matching pattern takes the most
8 # precedence. Previous matches will not be applied.
9
10
11 # PATH (can use glob) USERNAME(S)
12
13 passes/cmds/scratchpad.cc @nakengelhardt
14 frontends/rpc/ @whitequark
15 backends/cxxrtl/ @whitequark
16 passes/cmds/bugpoint.cc @whitequark
17 passes/techmap/flowmap.cc @whitequark
18 passes/opt/opt_lut.cc @whitequark
19
20
21 ## External Contributors
22 # Only users with write permission to the repository get review
23 # requests automatically, but we add information for other
24 # contributors here too, so we know who to ask to take a look.
25 # These still override previous lines, so be careful not to
26 # accidentally disable any of the above rules.
27
28 frontends/verilog/ @zachjs
29 frontends/ast/ @zachjs
30
31 techlibs/intel_alm/ @ZirconiumX
32
33 # pyosys
34 misc/*.py @btut
35
36 backends/firrtl @ucbjrl @azidar
37
38 passes/sat/qbfsat.cc @boqwxp
39 passes/sat/qbfsat.h @boqwxp
40 passes/cmds/exec.cc @boqwxp
41 passes/cmds/printattrs.cc @boqwxp