5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=cestrauss@gmail.com&emailassigned_to1=1&emailcc1=1&emailtype1=substring&resolution=---)
9 ## Currently working on
11 1. ALU CompUnit needs to recognise that RA (src1) can be zero
12 <https://bugs.libre-soc.org/show_bug.cgi?id=336>
14 Unit test Status: in progress
17 2. Something about the above (5), being optional.
18 <https://bugs.libre-soc.org/show_bug.cgi?id=336#c5>
20 Unit test Status: in progress
22 3. CompALUMulti parallel functions unit test
23 <https://bugs.libre-soc.org/show_bug.cgi?id=336#c11>
24 Priority: Medium-to-High
26 4. Code-morph LDSTCompUnit to use RecordObject structure, like CompUnitALU
27 <https://bugs.libre-soc.org/show_bug.cgi?id=318#c18>
28 Status: Need a review of Luke's implementation, compared to mine.
31 5. Test dual ports (two L0CacheBuffer with two ports, 4-4 as well) which
32 write to the same memory
33 <https://bugs.libre-soc.org/show_bug.cgi?id=318#c11>
37 6. Luke tried two LDs in the score6600 code - they failed.
38 <https://bugs.libre-soc.org/show_bug.cgi?id=318#c17>
39 Status: not started, need to check the [prototype] L0CacheBuffer
42 7. Fix a bug in the LDSTCompUnit
43 <https://bugs.libre-soc.org/show_bug.cgi?id=318>
44 Status: Luke thinks he fixed it, but needs a review and improving the
46 See: <https://bugs.libre-soc.org/show_bug.cgi?id=318#c7>
49 8. LDSTCompUnit parallel functions unit test
50 <https://bugs.libre-soc.org/show_bug.cgi?id=350>
53 11. Formal Proof for CompUnit
54 <https://bugs.libre-soc.org/show_bug.cgi?id=342>
56 12. Formal Proof for PartitionedSignal
57 <https://bugs.libre-soc.org/show_bug.cgi?id=565>
60 13. Implement simple VL for-loop in nMigen for TestIssuer
61 <https://bugs.libre-soc.org/show_bug.cgi?id=583>
64 ## Completed but not yet submitted:
66 1. FSM-based ALU example needed (compliant with ALU CompUnit)
67 <https://bugs.libre-soc.org/show_bug.cgi?id=417>
69 2. Fix MSB0 issues in the SVP64 Assembler, Simulator and Decoder
70 <https://bugs.libre-soc.org/show_bug.cgi?id=600>
72 ## Submitted for NLNet RFP
76 * [Bug #583](https://bugs.libre-soc.org/show_bug.cgi?id=583):
77 Implement simple VL for\-loop in nMigen for TestIssuer
78 * €2325 which is the total amount
79 * submitted on 2022-06-16
81 ### NLNet.2019.10.032.Formal
83 * [Bug #565](https://bugs.libre-soc.org/show_bug.cgi?id=565):
84 Improve formal verification on PartitionedSignal
85 * €2200 out of total of €3000
86 * submitted on 2022-06-16
88 ### NLNet.2019.10.046.Standards
90 * [Bug #588](https://bugs.libre-soc.org/show_bug.cgi?id=588):
91 add SVP64 to PowerDecoder2
92 * €300 out of total of €1000
93 * submitted on 2022-06-16
97 ### NLNet.2019.10.043.Wishbone
99 * [Bug #475](https://bugs.libre-soc.org/show_bug.cgi?id=475):
101 * Ran several Libre-SOC tests under cxxsim
102 * Helped isolate simulator issues by extracting a MVCE
103 (Minimal, Verifiable, Complete Example) in each case.
105 * €250 out of total of €1750