2 This file contains some very brief documentation on things like programming APIs.
3 Also consult the Yosys manual and the section about programming in the presentation.
4 (Both can be downloaded as PDF from the yosys webpage.)
7 --snip-- only the lines below this mark are included in the yosys manual --snip--
12 Outline of a Yosys command
13 --------------------------
15 Here is a the C++ code for a "hello_world" Yosys command (hello.cc):
17 #include "kernel/yosys.h"
20 PRIVATE_NAMESPACE_BEGIN
22 struct HelloWorldPass : public Pass {
23 HelloWorldPass() : Pass("hello_world") { }
24 virtual void execute(vector<string>, Design*) {
25 log("Hello World!\n");
31 This can be built into a Yosys module using the following command:
33 yosys-config --exec --cxx --cxxflags --ldflags -o hello.so -shared hello.cc --ldlibs
37 yosys-config --build hello.so hello.cc
39 And then executed using the following command:
41 yosys -m hello.so -p hello_world
47 Here is a short list of data structures that you should make yourself familiar
48 with before you write C++ code for Yosys. The following data structures are all
49 defined when "kernel/yosys.h" is included and USING_YOSYS_NAMESPACE is used.
51 1. Yosys Container Classes
53 Yosys uses dict<K, T> and pool<T> as main container classes. dict<K, T> is
54 essentially a replacement for std::unordered_map<K, T> and pool<T> is a
55 replacement for std::unordered_set<T>. The main characteristics are:
57 - dict<K, T> and pool<T> are about 2x faster than the std containers
59 - references to elements in a dict<K, T> or pool<T> are invalidated by
60 insert and remove operations (similar to std::vector<T> on push_back()).
62 - some iterators are invalidated by erase(). specifically, iterators
63 that have not passed the erased element yet are invalidated. (erase()
64 itself returns valid iterator to the next element.)
66 - no iterators are invalidated by insert(). elements are inserted at
67 begin(). i.e. only a new iterator that starts at begin() will see the
70 - the method .count(key, iterator) is like .count(key) but only
71 considers elements that can be reached via the iterator.
73 - iterators can be compared. it1 < it2 means that the position of t2
74 can be reached via t1 but not vice versa.
76 - the method .sort() can be used to sort the elements in the container
77 the container stays sorted until elements are added or removed.
79 - dict<K, T> and pool<T> will have the same order of iteration across
80 all compilers, standard libraries and architectures.
82 In addition to dict<K, T> and pool<T> there is also an idict<K> that
83 creates a bijective map from K to the integers. For example:
86 log("%d\n", si("hello")); // will print 42
87 log("%d\n", si("world")); // will print 43
88 log("%d\n", si.at("world")); // will print 43
89 log("%d\n", si.at("dummy")); // will throw exception
90 log("%s\n", si[42].c_str())); // will print hello
91 log("%s\n", si[43].c_str())); // will print world
92 log("%s\n", si[44].c_str())); // will throw exception
94 It is not possible to remove elements from an idict.
96 Finally mfp<K> implements a merge-find set data structure (aka. disjoint-set or
97 union-find) over the type K ("mfp" = merge-find-promote).
99 2. Standard STL data types
101 In Yosys we use std::vector<T> and std::string whenever applicable. When
102 dict<K, T> and pool<T> are not suitable then std::map<K, T> and std::set<T>
105 The types std::vector<T> and std::string are also available as vector<T>
106 and string in the Yosys namespace.
110 The current design (essentially a collection of modules, each defined by a
111 netlist) is stored in memory using RTLIL object (declared in kernel/rtlil.h,
112 automatically included by kernel/yosys.h). You should glance over at least
113 the declarations for the following types in kernel/rtlil.h:
116 This is a handle for an identifier (e.g. cell or wire name).
117 It feels a lot like a std::string, but is only a single int
118 in size. (The actual string is stored in a global lookup
122 A single signal bit. I.e. either a constant state (0, 1,
123 x, z) or a single bit from a wire.
126 Essentially a vector of SigBits.
130 The building blocks of the netlist in a module.
134 The module is a container with connected cells and wires
135 in it. The design is a container with modules in it.
137 All this types are also available without the RTLIL:: prefix in the Yosys
140 4. SigMap and other Helper Classes
142 There are a couple of additional helper classes that are in wide use
143 in Yosys. Most importantly there is SigMap (declared in kernel/sigtools.h).
145 When a design has many wires in it that are connected to each other, then a
146 single signal bit can have multiple valid names. The SigMap object can be used
147 to map SigSpecs or SigBits to unique SigSpecs and SigBits that consistently
148 only use one wire from such a group of connected wires. For example:
150 SigBit a = module->addWire(NEW_ID);
151 SigBit b = module->addWire(NEW_ID);
152 module->connect(a, b);
154 log("%d\n", a == b); // will print 0
156 SigMap sigmap(module);
157 log("%d\n", sigmap(a) == sigmap(b)); // will print 1
160 Using the RTLIL Netlist Format
161 ------------------------------
163 In the RTLIL netlist format the cell ports contain SigSpecs that point to the
164 Wires. There are no references in the other direction. This has two direct
167 (1) It is very easy to go from cells to wires but hard to go in the other way.
169 (2) There is no danger in removing cells from the netlists, but removing wires
170 can break the netlist format when there are still references to the wire
171 somewhere in the netlist.
173 The solution to (1) is easy: Create custom indexes that allow you to make fast
174 lookups for the wire-to-cell direction. You can either use existing generic
175 index structures to do that (such as the ModIndex class) or write your own
176 index. For many application it is simplest to construct a custom index. For
179 SigMap sigmap(module);
180 dict<SigBit, Cell*> sigbit_to_driver_index;
182 for (auto cell : module->cells())
183 for (auto &conn : cell->connections())
184 if (cell->output(conn.first))
185 for (auto bit : sigmap(conn.second))
186 sigbit_to_driver_index[bit] = cell;
188 Regarding (2): There is a general theme in Yosys that you don't remove wires
189 from the design. You can rename them, unconnect them, but you do not actually remove
190 the Wire object from the module. Instead you let the "clean" command take care
191 of the dangling wires. On the other hand it is safe to remove cells (as long as
192 you make sure this does not invalidate a custom index you are using in your code).
198 The following yosys commands are a good starting point if you are looking for examples
199 of how to use the Yosys API:
201 manual/CHAPTER_Prog/stubnets.cc
202 manual/PRESENTATION_Prog/my_cmd.cc
205 Notes on the existing codebase
206 ------------------------------
208 For historical reasons not all parts of Yosys adhere to the current coding
209 style. When adding code to existing parts of the system, adhere to this guide
210 for the new code instead of trying to mimic the style of the surrounding code.
221 - Yosys code is using tabs for indentation. Tabs are 8 characters.
223 - A continuation of a statement in the following line is indented by
226 - Lines are as long as you want them to be. A good rule of thumb is
227 to break lines at about column 150.
229 - Opening braces can be put on the same or next line as the statement
230 opening the block (if, switch, for, while, do). Put the opening brace
231 on its own line for larger blocks, especially blocks that contains
234 - Otherwise stick to the Linux Kernel Coding Style:
235 https://www.kernel.org/doc/Documentation/CodingStyle
241 Yosys is written in C++11. At the moment only constructs supported by
242 gcc 4.8 are allowed in Yosys code. This will change in future releases.
244 In general Yosys uses "int" instead of "size_t". To avoid compiler
245 warnings for implicit type casts, always use "GetSize(foobar)" instead
246 of "foobar.size()". (GetSize() is defined in kernel/yosys.h)
248 Use range-based for loops whenever applicable.
251 --snap-- only the lines above this mark are included in the yosys manual --snap--
254 Creating the Visual Studio Template Project
255 ===========================================
257 1. Create an empty Visual C++ Win32 Console App project
259 Microsoft Visual Studio Express 2013 for Windows Desktop
260 Open New Project Wizard (File -> New Project..)
262 Project Name: YosysVS
263 Solution Name: YosysVS
264 [X] Create directory for solution
265 [ ] Add to source control
267 [X] Console applications
271 2. Open YosysVS Project Properties
273 Select Configuration: All Configurations
275 C/C++ -> General -> Additional Include Directories
278 C/C++ -> Preprocessor -> Preprocessor Definitions
279 Add: _YOSYS_;_CRT_SECURE_NO_WARNINGS
281 3. Resulting file system tree:
285 YosysVS/YosysVS/YosysVS.vcxproj
286 YosysVS/YosysVS/YosysVS.vcxproj.filters
289 YosysVS/YosysVS.v12.suo
291 4. Zip YosysVS as YosysVS-Tpl-v1.zip
295 Checklist for adding internal cell types
296 ========================================
298 Things to do right away:
300 - Add to kernel/celltypes.h (incl. eval() handling for non-mem cells)
301 - Add to InternalCellChecker::check() in kernel/rtlil.cc
302 - Add to techlibs/common/simlib.v
303 - Add to techlibs/common/techmap.v
305 Things to do after finalizing the cell interface:
307 - Add support to kernel/satgen.h for the new cell type
308 - Add to manual/CHAPTER_CellLib.tex (or just add a fixme to the bottom)
309 - Maybe add support to the Verilog backend for dumping such cells as expression
313 Checklist for creating Yosys releases
314 =====================================
316 Update the CHANGELOG file:
323 Update and check documentation:
328 - sanity check the figures in the appnotes and presentation
329 - if there are any odd things -> investigate
330 - make cosmetic changes to the .tex files if necessary
333 vi README CodingReadme
334 - is the information provided in those file still up to date
337 Then with default config setting:
343 ./yosys -p 'proc; show' tests/simple/fiedler-cooley.v
344 ./yosys -p 'proc; opt; show' tests/simple/fiedler-cooley.v
345 ./yosys -p 'synth; show' tests/simple/fiedler-cooley.v
346 ./yosys -p 'synth_xilinx -top up3down5; show' tests/simple/fiedler-cooley.v
348 cd ~yosys/examples/cmos
351 cd ~yosys/examples/basys3
355 Test building plugins with various of the standard passes:
357 yosys-config --build test.so equiv_simple.cc
358 - also check the code examples in CodingReadme
361 And if a version of the verific library is currently available:
364 cat frontends/verific/build_amd64.txt
365 - follow instructions
368 ../../yosys test_navre.ys
371 Finally run all tests with "make config-{clang,gcc,gcc-4.8}":
384 make purge gen_issues gen_samples
385 make SYN_LIST="yosys" SIM_LIST="icarus yosim verilator" REPORT_FULL=1 world
386 chromium-browser report.html
391 - set YOSYS_VER to x.y.z in Makefile
392 - update version string in CHANGELOG
393 git commit -am "Yosys x.y.z"
396 - post changelog on github
397 - post short release note on reddit
400 Updating the website:
406 - update pdf files on the website
411 git commit -am update