3 * (Originally at <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000146.html>)
4 * [alu_fsm.py source](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/alu_fsm.py;h=9668535aedc8e507212906baf679dc37484b8e8d;hb=1d4fa2db3d660510ebeceb650188c6fcf3127fd4#l209)
6 Lately, I've been investigating about generating better GTKWave "save"
7 files (\*.gtkw), from Python. The goal is to ease analysis of traces
8 generated by unit-tests, and at the same time to better understand the
9 inner working of modules, for which we are writing such tests.
11 I am using src/soc/experiment/alu_fsm.py as a test bed for demonstration.
13 To see the current work, run:
15 1) python3 src/soc/experiment/alu_fsm.py
16 2) gtkwave test_shifter.gtkw
18 Besides color, another interesting feature is collapsible group of
19 traces. Try selecting the opening brace of the "debug" and "internal"
20 groups, and double-click or press T.
22 Another bonus is string traces, which allows "printf" style debugging in
25 A current limitation is having to deal with signal names instead of
26 Signals themselves. Also, direct use of vcd.gtkw is a bit verbose. I
27 intend to work a bit on this, next.
29 Possibly, I'll propose and contribute back improvements to the nMigen
30 sim.pysim.Simulator.write_vcd method, which was my inspiration for this
33 A more complete description follows:
35 https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=de64658d0a482f1d6df3c84b4087864ff65ccfef
37 commit de64658d0a482f1d6df3c84b4087864ff65ccfef
38 Author: Cesar Strauss <cestrauss@gmail.com>
39 Date: Thu Aug 13 19:40:35 2020 -0300
41 Demonstrates creating stylish GTKWave "save" files from python
43 This is inspired on the use of the vcd.gtkw module in nMigen, used
44 internally to create "save" files of selected Signals, for
45 "Simulator.write_vcd".
47 However, the vcd.gtkw module exposes a great deal of extra
50 1) Individual trace colors.
51 For instance, use different color styles for input, output, debug
53 2) Numeric bases besides the default hex.
54 3) Collapsible trace groups
55 Useful to hide and show, at once, groups of debug, internal and
57 Select the opening or closing brace, then use the T key.
58 4) Comments in the signal names pane
59 5) Change the displayed name of a trace
60 6) Sane default for initial zoom level
61 7) Place markers on interesting places
62 8) Put the generating file name as a comment in the file
64 https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=d3a72bb0688cf343dddc069ef50ba60b9736e8d9
66 commit d3a72bb0688cf343dddc069ef50ba60b9736e8d9
67 Author: Cesar Strauss <cestrauss@gmail.com>
68 Date: Fri Aug 14 08:06:49 2020 -0300
70 Demonstrates adding extra debug signals traces to the dump file
72 At simulation time, you can declare a new signal, and use it inside
73 the test case, as any other signal. By including it in the "traces"
74 parameter of Simulator.write_vcd, it is included in the trace dump
77 Useful for adding "printf" style debugging for GTKWave.
79 https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=1d4fa2db3d660510ebeceb650188c6fcf3127fd4
81 commit 1d4fa2db3d660510ebeceb650188c6fcf3127fd4 (HEAD -> master,
82 origin/master, origin/HEAD)
83 Author: Cesar Strauss <cestrauss@gmail.com>
84 Date: Fri Aug 14 08:25:36 2020 -0300
86 Demonstrates string traces
88 When declaring a Signal, you can pass a custom decoder that
89 translates the Signal logic level to a string. nMigen uses this
90 internally to display Enum traces, but it is available for general
93 Some applications are:
94 1) Display a string when a signal is at high level, otherwise show a
95 single horizontal line. Useful to draw attention to a time interval.
96 2) Display the stages of a unit test
97 3) Display arbitrary debug statements along the timeline.