HDL_workflow/ECP5_FPGA.mdwn

   1 # ULX3S JTAG Connection with ft232r
   2
   3 Cross referenced with:
   4
   5 <https://bugs.libre-soc.org/show_bug.cgi?id=517>
   6
   7 <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html>
   8
   9 <https://www.amazon.co.uk/DSD-TECH-adapter-FT232RL-Compatible/dp/B07BBPX8B8/ref=sr_1_11?dchild=1&keywords=ft232&qid=1632498288&s=amazon-devices&sr=1-11>
  10
  11 <https://www.amazon.co.uk/Elegoo-120pcs-Multicolored-Breadboard-arduino-colorful/dp/B01EV70C78/ref=asc_df_B01EV70C78/?tag=googshopuk-21&linkCode=df0&hvadid=310773493424&hvpos=&hvnetw=g&hvrand=6539073631118556110&hvpone=&hvptwo=&hvqmt=&hvdev=m&hvdvcmdl=&hvlocint=&hvlocphy=1006886&hvtargid=pla-362913641420&psc=1>
  12 ## Original Instructions
  13
  14 See <https://bugs.libre-soc.org/show_bug.cgi?id=517#c0>
  15
  16 Checklist based on above
  17
  18 * For god's sake make sure you get this right, ***TRIPLE*** check everything.
  19
  20 * ***DO*** make sure to ***only*** drive an input as an input, and to ***only*** drive an output as an output.
  21
  22 * ***DO*** make sure to ***only*** wire up 3.3V to 3.3V and to ***only*** wire up GND to GND with the jumper-cables.
  23
  24 * ***DO*** make sure that ***before*** even ***thinking*** of uploading to and powering up the FPGA that everything has been ***THOROUGHLY*** triple-checked.
  25
  26 If you violate any of the above stated hard-and-fast rules you will end up learning the hard way by **DESTROYING** the FPGA.
  27
  28 To start we have to ensure we have a safe set up.
  29
  30 | Checklist Step |
  31 |----------------|
  32 | Ensure power is disconnected from FPGA |
  33 | Ensure ft232r USB is disconnected |
  34 | Ensure FPGA USB is disconnected |
  35
  36 Now lets review all of the relevant material on this page before we begin the wiring process.
  37
  38 | Checklist Step |
  39 |----------------|
  40 | Review the ft232r Connector diagram and table |
  41 | Review the connections table for your model of fpga |
  42 | Ensure the orientation of the FPGA and ft232r match that of the images and diagrams on this page |
  43
  44 Next we will wire up the ft232r and our FPGA in three separate stages.
  45
  46 * First we will attach one end of a ***MALE-TO-MALE (MTM)*** jumper cable to each necessary female header pin-hole on the ft232f.
  47
  48 * Then we will attach one end of a ***FEMALE-TO-FEMALE (FTF)*** cable to each male header pin on the FPGA.
  49
  50 * Finally, we will connect the wires from the ft232r to the wires from the FPGA by matching the colours of the wires.
  51
  52 This way you do not lose the connections when you want to disconnect and store the two devices. We are using FEMALE-TO-FEMALE jumper cables on the male header pins of the FPGA so that the wires do not randomly damage the bare PCB due to a short.
  53
  54 We will wire each of the pins on the the ft232r according to the diagrams, tables, and images on this page.
  55
  56 |   Action   | Colour | Pin Name |
  57 |------------|--------|----------|
  58 | Attach MTM | Black  |   GND    |
  59 | Attach MTM | Brown  |   TMS    |
  60 | Attach MTM | Red    |   VCC    |
  61 | Attach MTM | Orange |   TCK    |
  62 | Attach MTM | Yellow |   TDI    |
  63 | Attach MTM | Green  |   TDO    |
  64
  65 Next, we will wire each of the pins on the the FPGA according to the diagrams, tables, and images on this page.
  66
  67 Follow this section if you have the ULX3S FPGA:
  68
  69 |   Action   | Colour | Pin # | Pin Name |
  70 |------------|--------|-------|----------|
  71 | Attach FTF | Red    |   2   |   VREF   |
  72 | Attach FTF | Black  |   4   |   GND    |
  73 | Attach FTF | Yellow |   5   |   TDI    |
  74 | Attach FTF | Brown  |   6   |   TMS    |
  75 | Attach FTF | Orange |   7   |   TCK    |
  76 | Attach FTF | Green  |   8   |   TDO    |
  77
  78 Follow this section if you have the Versa ECP5 FPGA:
  79
  80 |   Action   | Colour | X3 Pin # | Pin Name |
  81 |------------|--------|----------|----------|
  82 | Attach FTF | Red    |    39    |   VREF   |
  83 | Attach FTF | Black  |     1    |   GND    |
  84 | Attach FTF | Yellow |     4    |   TDI    |
  85 | Attach FTF | Brown  |     5    |   TMS    |
  86 | Attach FTF | Orange |     6    |   TCK    |
  87 | Attach FTF | Green  |     7    |   TDO    |
  88
  89 Final steps for both FPGA boards:
  90
  91 | Checklist Step |
  92 |----------------|
  93 | Check each jumper wire connection between the corresponding pins on the FPGA and the ft232r **THREE** times |
  94 | ***lckl*** check for ground loops? |
  95
  96
  97 Finally, we will connect the jumper cables of the same colour from ft232r and the FPGA.
  98
  99 | Checklist Step |
 100 |----------------|
 101 | Attach the ends of the **RED** jumper cables    |
 102 | Attach the ends of the **BLACK** jumper cables  |
 103 | Attach the ends of the **YELLOW** jumper cables |
 104 | Attach the ends of the **BROWN** jumper cables  |
 105 | Attach the ends of the **ORANGE** jumper cables |
 106 | Attach the ends of the **GREEN** jumper cables  |
 107
 108 ***lckl if both the micro-usb cable and the ft232r GND and VCC wires are connected to the fpga will this result in volatage fighting where the fpga will be damaged?***
 109
 110 Finally, plug in the USB end of the USB-to-MicroUSB cable that is plugged into the ft232r into your computer. Begin testing the SOC on the FPGA (instructions to follow).
 111
 112 ## Connecting the dots:
 113
 114 Accurate render of board for reference <https://github.com/emard/ulx3s/blob/master/pic/ulx3st.jpg>
 115
 116 Litex platform file <https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py>
 117
 118     ("gpio", 0,
 119         Subsignal"p", Pins("B11")),
 120         Subsignal("n", Pins("C11")),
 121         IOStandard("LVCMOS33")
 122     ),
 123     ("gpio", 1,
 124         Subsignal("p", Pins("A10")),
 125         Subsignal("n", Pins("A11")),
 126         IOStandard("LVCMOS33")
 127     ),
 128
 129 ULX3S FPGA constraints file <https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342>
 130
 131     LOCATE COMP "gp[0]" SITE "B11"; # J1_5+  GP0 PCLK
 132     LOCATE COMP "gn[0]" SITE "C11"; # J1_5-  GN0 PCLK
 133     LOCATE COMP "gp[1]" SITE "A10"; # J1_7+  GP1 PCLK
 134     LOCATE COMP "gn[1]" SITE "A11"; # J1_7-  GN1 PCLK
 135
 136 ULX3S FPGA Schematic <https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf>
 137
 138 ```
 139 J1 J2 PIN number 1-40 is for FEMALE 90° ANGLED header.
 140 For MALE VERTICAL header, SWAP EVEN and ODD pin numbers.
 141
 142                     J1
 143
 144  Label  [GP{x}]|PCB pin label|[GN{x}] Label
 145            (Pin count +)(Pin count -)
 146 _________________V__________V________________
 147  IO VOLT REF 3V3 2  |3.3V|  1  NOT CONNECTED
 148            [GND] 4  | -| |  3  NOT CONNECTED
 149 PCLKT0_0   [GP0] 6  |  0 |  5  [GN0] PCLKC0_0
 150 PCLKT0_1   [GP1] 8  |  1 |  7  [GN1] PCLKC0_1
 151
 152
 153 GP,GN 0-7 single-ended connected to Bank0
 154 GP,GN 8-13 differential bidirectional connected to BANK7
 155 ```
 156
 157 Connecting all the dots:
 158
 159 ```
 160 Board pin # (count) | Board pin label # | FPGA IO PAD | GPIO # (n/p) |   Label  |
 161       5 (J1_5-)     |         0         |      C11    |    gn[0]     | PCLKC0_0 |
 162       6 (J1_5+)     |         0         |      B11    |    gp[0]     | PCLKT0_0 |
 163       7 (J1_7-)     |         1         |      A11    |    gn[1]     | PCLKC0_1 |
 164       8 (J1_7+)     |         1         |      A10    |    gp[1]     | PCLKT0_1 |
 165 ```
 166
 167 As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs.
 168
 169 ``` from http://openocd.org/doc/html/Debug-Adapter-Configuration.html#index-ftdi
 170 List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
 171
 172     - RXD(5) - TDI
 173     - TXD(1) - TCK
 174     - RTS(3) - TDO
 175     - CTS(11) - TMS
 176     - DTR(2) - TRST
 177     - DCD(10) - SRST
 178 ```
 179
 180 ``` from https://github.com/ntfreak/openocd/blob/master/src/jtag/drivers/ft232r.c#L79-L99
 181 /**
 182  * FT232R GPIO bit number to RS232 name
 183  */
 184 #define FT232R_BIT_COUNT 8
 185 static char *ft232r_bit_name_array[FT232R_BIT_COUNT] = {
 186         "TXD", /* 0: pin 1  TCK output */
 187         "RXD", /* 1: pin 5  TDI output */
 188         "RTS", /* 2: pin 3  TDO input */
 189         "CTS", /* 3: pin 11 TMS output */
 190         "DTR", /* 4: pin 2  /TRST output */
 191         "DSR", /* 5: pin 9  unused */
 192         "DCD", /* 6: pin 10 /SYSRST output */
 193         "RI"   /* 7: pin 6  unused */
 194 };
 195
 196 static int tck_gpio; /* initialized to 0 by default */
 197 static int tdi_gpio = 1;
 198 static int tdo_gpio = 2;
 199 static int tms_gpio = 3;
 200 static int ntrst_gpio = 4;
 201 static int nsysrst_gpio = 6;
 202 ```
 203
 204 ```from ft232 usb to 6 pin female header manual
 205
 206 ft232 pin and wire colour table converted to jtag signal names:
 207
 208 ```
 209 |-------|------|--------|----------|
 210 | Pin # | JTAG |  FT232 | Colour   |
 211 |-------|------|--------|----------|
 212 |   1   | VCC  | VCC    |  Red     |
 213 |   2   | GND  | GND    |  Black   |
 214 |   3   | TCK  | TXD    |  White   |
 215 |   4   | TDI  | RXD    |  Green   |
 216 |   5   | TDO  | RTS    |  Yellow  |
 217 |   6   | TMS  | CTS    |  Blue    |
 218 |-------|------|--------|----------|
 219 ```
 220 Proposed FPGA External Pin to ft232r JTAG pin connections:
 221
 222 ```
 223    all pin #'s have headers pins on the fpga unless denoted as (no header)
 224  ______________________________________________________________________________
 225 |             | board |             |             |                |           |
 226 |             | label |             |             | ft232r   JTAG  |           |
 227 |    pin #    |   #   | FPGA IO PAD |GPIO # (n/p) | Pin #  (Signal)|Wire Colour|
 228 |_____________|_______|_____________|_____________|________________|___________|
 229 |1 (no header)|  3.3v |NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
 230 |2            |  3.3v | IO VOLT REF | IO VOLT REF |    3 (VCC)     |    Red    |
 231 |3 (no header)|-|(GND)|NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
 232 |4            |-|(GND)|    NONE     |     GND     |    1 (GND)     |   Black   |
 233 |5 (J1_5-)    |   0   |     C11     |    gn[0]    |    5 (TDI)     |   Green   |
 234 |6 (J1_5+)    |   0   |     B11     |    gp[0]    |    2 (TMS)     |   Blue    |
 235 |7 (J1_7-)    |   1   |     A11     |    gn[1]    |    4 (TCK)     |   White   |
 236 |8 (J1_7+)    |   1   |     A10     |    gp[1]    |    6 (TDO)     |   Yellow  |
 237 |_____________|_______|_____________|_____________|________________|___________|
 238 ```
 239
 240 Complete diagram:
 241
 242 ```
 243 Pins intentionally have no header or are not connected to the ft232 are marked
 244 and therefore have no value are marked with 'NOT'
 245
 246 (ft232r# JTAG) = (ft232r pin #   JTAG signal name)
 247
 248                              J1
 249             Wire                             Wire
 250            Colour [GP{x}]|PCB label|[GN{x}] Colour
 251 (ft232r# JTAG)   (Pin count +)(Pin count -)   (ft232r# JTAG)
 252  ______________________V__________V_______________________
 253 |                                                         |
 254 |(3 VCC) red    [VREF] 2  |3.3V|  1   NOT   NOT    NOT    |
 255 |(1 GND) black   [GND] 4  | -| |  3   NOT   NOT    NOT    |
 256 |(2 TMS) Blue    [GP0] 6  |  0 |  5  [GN0] Green  (5 TDI) |
 257 |(6 TDO) Yellow  [GP1] 8  |  1 |  7  [GN1] White  (4 TCK) |
 258 |_________________________________________________________|
 259 ```
 260
 261 ## Images of wires on ulx3s FPGA and on ft232r (lkcl to update images for Versa ECP5)
 262
 263 Image of JTAG jumper wire connections on ULX3S FPGA side:
 264
 265 [[!img HDL_workflow/ulx3s_fpga_jtag_wires.jpg size="500x" ]]
 266
 267 Image of JTAG jumper wire connections on ft232r side:
 268
 269 [[!img HDL_workflow/ft232r_jtag_wires.jpg size="500x" ]]
 270
 271 Colour markings on ft232r side:
 272
 273 [[!img HDL_workflow/ft232.png size="500x" ]]
 274
 275 # VERSA ECP5 Connections
 276
 277 Table of connections:
 278
 279 | X3  pin #   | FPGA IO PAD |  Function | FT232  | Wire Colour|
 280 |-------------|-------------|-----------|--------|------------|
 281 |   39 +3.3V  | 3.3V supply |    (VCC)  | VREF   |   Red      |
 282 |    1 GND    |     GND     |    (GND)  | GND    |   Black    |
 283 |    4 IO29   |     B19     |    (TDI)  | RXD    |   Green    |
 284 |    5 IO30   |     B12     |    (TMS)  | CTS    |   Blue     |
 285 |    6 IO31   |     B9      |    (TCK)  | TXD    |   White    |
 286 |    7 IO32   |     E6      |    (TDO)  | RTS    |   Yellow   |
 287
 288 [[!img 2020-11-03_13-22.png size="900x" ]]
 289
 290 [[!img 2020-11-03_13-25.png size="900x" ]]
 291
 292 [[!img versa_ecp5_x3_connector.jpg size="900x" ]]
 293