1 # ULX3S JTAG Connection with ft232r
5 <https://bugs.libre-soc.org/show_bug.cgi?id=517>
7 <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html>
9 ## Original Instructions
11 See <https://bugs.libre-soc.org/show_bug.cgi?id=517#c0>
13 Checklist based on above
15 * For god's sake make sure you get this right, ***TRIPLE*** check everything.
17 * ***DO*** make sure to ***only*** drive an input as an input, and to ***only*** drive an output as an output.
19 * ***DO*** make sure to ***only*** wire up 3.3V to 3.3V and to ***only*** wire up GND to GND with the jumper-cables.
21 * ***DO*** make sure that ***before*** even ***thinking*** of uploading to and powering up the FPGA that everything has been ***THOROUGHLY*** triple-checked.
23 If you violate any of the above stated hard-and-fast rules you will end up learning the hard way by **DESTROYING** the FPGA.
25 To start we have to ensure we have a safe set up.
29 | Ensure power is disconnected from FPGA |
30 | Ensure ft232r USB is disconnected |
31 | Ensure FPGA USB is disconnected |
33 Now lets review all of the relevant material on this page before we begin the wiring process.
37 | Review the ft232r Connector diagram and table |
38 | Review the connections table for your model of fpga |
39 | Ensure the orientation of the FPGA and ft232r match that of the images and diagrams on this page |
41 Next we will wire up the ft232r and our FPGA in three separate stages.
43 * First we will attach one end of a ***MALE-TO-MALE (MTM)*** jumper cable to each necessary female header pin-hole on the ft232f.
45 * Then we will attach one end of a ***FEMALE-TO-FEMALE (FTF)*** cable to each male header pin on the FPGA.
47 * Finally, we will connect the wires from the ft232r to the wires from the FPGA by matching the colours of the wires.
49 This way you do not lose the connections when you want to disconnect and store the two devices. We are using FEMALE-TO-FEMALE jumper cables on the male header pins of the FPGA so that the wires do not randomly damage the bare PCB due to a short.
51 We will wire each of the pins on the the ft232r according to the diagrams, tables, and images on this page.
53 | Action | Colour | Pin Name |
54 |------------|--------|----------|
55 | Attach MTM | Black | GND |
56 | Attach MTM | Brown | TMS |
57 | Attach MTM | Red | VCC |
58 | Attach MTM | Orange | TCK |
59 | Attach MTM | Yellow | TDI |
60 | Attach MTM | Green | TDO |
62 Next, we will wire each of the pins on the the FPGA according to the diagrams, tables, and images on this page.
64 Follow this section if you have the ULX3S FPGA:
66 | Action | Colour | Pin # | Pin Name |
67 |------------|--------|-------|----------|
68 | Attach FTF | Red | 2 | VREF |
69 | Attach FTF | Black | 4 | GND |
70 | Attach FTF | Yellow | 5 | TDI |
71 | Attach FTF | Brown | 6 | TMS |
72 | Attach FTF | Orange | 7 | TCK |
73 | Attach FTF | Green | 8 | TDO |
75 Follow this section if you have the Versa ECP5 FPGA:
77 | Action | Colour | X3 Pin # | Pin Name |
78 |------------|--------|----------|----------|
79 | Attach FTF | Red | 39 | VREF |
80 | Attach FTF | Black | 1 | GND |
81 | Attach FTF | Yellow | 4 | TDI |
82 | Attach FTF | Brown | 5 | TMS |
83 | Attach FTF | Orange | 6 | TCK |
84 | Attach FTF | Green | 7 | TDO |
86 Final steps for both FPGA boards:
90 | Check each jumper wire connection between the corresponding pins on the FPGA and the ft232r **THREE** times |
91 | ***lckl*** check for ground loops? |
94 Finally, we will connect the jumper cables of the same colour from ft232r and the FPGA.
98 | Attach the ends of the **RED** jumper cables |
99 | Attach the ends of the **BLACK** jumper cables |
100 | Attach the ends of the **YELLOW** jumper cables |
101 | Attach the ends of the **BROWN** jumper cables |
102 | Attach the ends of the **ORANGE** jumper cables |
103 | Attach the ends of the **GREEN** jumper cables |
105 ***lckl if both the micro-usb cable and the ft232r GND and VCC wires are connected to the fpga will this result in volatage fighting where the fpga will be damaged?***
107 Finally, plug in the USB end of the USB-to-MicroUSB cable that is plugged into the ft232r into your computer. Begin testing the SOC on the FPGA (instructions to follow).
109 ## Connecting the dots:
111 Accurate render of board for reference <https://github.com/emard/ulx3s/blob/master/pic/ulx3st.jpg>
113 Litex platform file <https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py>
116 Subsignal"p", Pins("B11")),
117 Subsignal("n", Pins("C11")),
118 IOStandard("LVCMOS33")
121 Subsignal("p", Pins("A10")),
122 Subsignal("n", Pins("A11")),
123 IOStandard("LVCMOS33")
126 ULX3S FPGA constraints file <https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342>
128 LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 PCLK
129 LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 PCLK
130 LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 PCLK
131 LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 PCLK
133 ULX3S FPGA Schematic <https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf>
136 J1 J2 PIN number 1-40 is for FEMALE 90° ANGLED header.
137 For MALE VERTICAL header, SWAP EVEN and ODD pin numbers.
141 Label [GP{x}]|PCB pin label|[GN{x}] Label
142 (Pin count +)(Pin count -)
143 _________________V__________V________________
144 IO VOLT REF 3V3 2 |3.3V| 1 NOT CONNECTED
145 [GND] 4 | -| | 3 NOT CONNECTED
146 PCLKT0_0 [GP0] 6 | 0 | 5 [GN0] PCLKC0_0
147 PCLKT0_1 [GP1] 8 | 1 | 7 [GN1] PCLKC0_1
150 GP,GN 0-7 single-ended connected to Bank0
151 GP,GN 8-13 differential bidirectional connected to BANK7
154 Connecting all the dots:
157 Board pin # (count) | Board pin label # | FPGA IO PAD | GPIO # (n/p) | Label |
158 5 (J1_5-) | 0 | C11 | gn[0] | PCLKC0_0 |
159 6 (J1_5+) | 0 | B11 | gp[0] | PCLKT0_0 |
160 7 (J1_7-) | 1 | A11 | gn[1] | PCLKC0_1 |
161 8 (J1_7+) | 1 | A10 | gp[1] | PCLKT0_1 |
164 As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs.
166 ``` from http://openocd.org/doc/html/Debug-Adapter-Configuration.html#index-ftdi
167 List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
177 ``` from https://github.com/ntfreak/openocd/blob/master/src/jtag/drivers/ft232r.c#L79-L99
179 * FT232R GPIO bit number to RS232 name
181 #define FT232R_BIT_COUNT 8
182 static char *ft232r_bit_name_array[FT232R_BIT_COUNT] = {
183 "TXD", /* 0: pin 1 TCK output */
184 "RXD", /* 1: pin 5 TDI output */
185 "RTS", /* 2: pin 3 TDO input */
186 "CTS", /* 3: pin 11 TMS output */
187 "DTR", /* 4: pin 2 /TRST output */
188 "DSR", /* 5: pin 9 unused */
189 "DCD", /* 6: pin 10 /SYSRST output */
190 "RI" /* 7: pin 6 unused */
193 static int tck_gpio; /* initialized to 0 by default */
194 static int tdi_gpio = 1;
195 static int tdo_gpio = 2;
196 static int tms_gpio = 3;
197 static int ntrst_gpio = 4;
198 static int nsysrst_gpio = 6;
201 ```from ft232 usb to 6 pin female header manual
203 ft232 pin and wire colour table converted to jtag signal names:
206 |-------|------|--------|----------|
207 | Pin # | JTAG | FT232 | Colour |
208 |-------|------|--------|----------|
209 | 1 | VCC | VCC | Red |
210 | 2 | GND | GND | Black |
211 | 3 | TCK | TXD | White |
212 | 4 | TDI | RXD | Green |
213 | 5 | TDO | RTS | Yellow |
214 | 6 | TMS | CTS | Blue |
215 |-------|------|--------|----------|
217 Proposed FPGA External Pin to ft232r JTAG pin connections:
220 all pin #'s have headers pins on the fpga unless denoted as (no header)
221 ______________________________________________________________________________
223 | | label | | | ft232r JTAG | |
224 | pin # | # | FPGA IO PAD |GPIO # (n/p) | Pin # (Signal)|Wire Colour|
225 |_____________|_______|_____________|_____________|________________|___________|
226 |1 (no header)| 3.3v |NOT CONNECTED|NOT CONNECTED| NOT CONNECTED | NOT |
227 |2 | 3.3v | IO VOLT REF | IO VOLT REF | 3 (VCC) | Red |
228 |3 (no header)|-|(GND)|NOT CONNECTED|NOT CONNECTED| NOT CONNECTED | NOT |
229 |4 |-|(GND)| NONE | GND | 1 (GND) | Black |
230 |5 (J1_5-) | 0 | C11 | gn[0] | 5 (TDI) | Green |
231 |6 (J1_5+) | 0 | B11 | gp[0] | 2 (TMS) | Blue |
232 |7 (J1_7-) | 1 | A11 | gn[1] | 4 (TCK) | White |
233 |8 (J1_7+) | 1 | A10 | gp[1] | 6 (TDO) | Yellow |
234 |_____________|_______|_____________|_____________|________________|___________|
240 Pins intentionally have no header or are not connected to the ft232 are marked
241 and therefore have no value are marked with 'NOT'
243 (ft232r# JTAG) = (ft232r pin # JTAG signal name)
247 Colour [GP{x}]|PCB label|[GN{x}] Colour
248 (ft232r# JTAG) (Pin count +)(Pin count -) (ft232r# JTAG)
249 ______________________V__________V_______________________
251 |(3 VCC) red [VREF] 2 |3.3V| 1 NOT NOT NOT |
252 |(1 GND) black [GND] 4 | -| | 3 NOT NOT NOT |
253 |(2 TMS) Blue [GP0] 6 | 0 | 5 [GN0] Green (5 TDI) |
254 |(6 TDO) Yellow [GP1] 8 | 1 | 7 [GN1] White (4 TCK) |
255 |_________________________________________________________|
258 ## Images of wires on ulx3s FPGA and on ft232r (lkcl to update images for Versa ECP5)
260 Image of JTAG jumper wire connections on ULX3S FPGA side:
262 [[!img HDL_workflow/ulx3s_fpga_jtag_wires.jpg size="500x" ]]
264 Image of JTAG jumper wire connections on ft232r side:
266 [[!img HDL_workflow/ft232r_jtag_wires.jpg size="500x" ]]
268 Colour markings on ft232r side:
270 [[!img HDL_workflow/ft232.png size="500x" ]]
272 # VERSA ECP5 Connections
274 Table of connections:
276 | X3 pin # | FPGA IO PAD | Function | FT232 | Wire Colour|
277 |-------------|-------------|-----------|--------|------------|
278 | 39 +3.3V | 3.3V supply | (VCC) | VREF | Red |
279 | 1 GND | GND | (GND) | GND | Black |
280 | 4 IO29 | B19 | (TDI) | RXD | Green |
281 | 5 IO30 | B12 | (TMS) | CTS | Blue |
282 | 6 IO31 | B9 | (TCK) | TXD | White |
283 | 7 IO32 | E6 | (TDO) | RTS | Yellow |
285 [[!img 2020-11-03_13-22.png size="900x" ]]
287 [[!img 2020-11-03_13-25.png size="900x" ]]
289 [[!img versa_ecp5_x3_connector.jpg size="900x" ]]