HDL_workflow/ECP5_FPGA.mdwn

   1 # ULX3S JTAG Connection with STLINKV2
   2
   3 Cross referenced with:
   4
   5 <https://bugs.libre-soc.org/show_bug.cgi?id=517>
   6
   7 <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html>
   8
   9 ## Original Instructions
  10
  11 See <https://bugs.libre-soc.org/show_bug.cgi?id=517#c0>
  12
  13 Checklist based on above
  14
  15 * For god's sake make sure you get this right, ***TRIPLE*** check everything.
  16
  17 * ***DO*** make sure to ***only*** drive an input as an input, and to ***only*** drive an output as an output.
  18
  19 * ***DO*** make sure to ***only*** wire up 5.0V to 5.0V and to ***only*** wire up GND to GND with the jumper-cables.
  20
  21 * ***DO*** make sure that ***before*** even ***thinking*** of uploading to and powering up the FPGA that everything has been ***THOROUGHLY*** triple-checked.
  22
  23 If you violate any of the above stated hard-and-fast rules you will end up learning the hard way by **DESTROYING** the FPGA.
  24
  25 To start we have to ensure we have a safe set up.
  26
  27 | Done?   | Checklist Step |
  28 |---------|----------------|
  29 |         | Ensure power is disconnected from FPGA |
  30 |         | Ensure STLINKV2 USB is disconnected |
  31 |         | Ensure FPGA USB is disconnected |
  32
  33 Now lets review all of the relevant material on this page before we begin the wiring process.
  34
  35 | Done?   | Checklist Step |
  36 |---------|----------------|
  37 |         | Review the STLINKv2 Connector diagram and table |
  38 |         | Review the connections table for your model of fpga |
  39 |         | Make sure the orientation of your FPGA board and your STLINKv2 are the same as the images and diagrams on this page |
  40
  41 Next we will wire up the STLINKv2 and our FPGA in three separate stages. First attaching the FEMALE end of a FEMALE-TO-MALE jumper cable to each male header pins on the STLINKv2. Then we will attach a ***COMPLETELY DIFFERENT*** FEMALE-TO-FEMALE jumper cable to each male header pin on the FPGA. Finally, we will connect the wires from the STLINKv2 to the wires from the FPGA by matching the colours of the wires. This way you do not lose the connections when you want to disconnect and store the two devices. We are using FEMALE-TO-FEMALE jumper cables on the male header pins of each of the FPGA so that the wires do not randomly damage the bare PCB due to a short.
  42
  43 We will wire each of the pins on the the STLINKv2 according to the diagrams, tables, and images on this page.
  44
  45 | Done?   | Checklist Step |
  46 |---------|----------------|
  47 |         | Attach the FEMALE end of a FEMALE-TO-MALE **RED** jumper cable to (**STLINKv2 pin #2**), this will serve as the **Voltage Reference** signal (**VREF**)
  48 |         | Attach the FEMALE end of a FEMALE-TO-MALE **BLACK** jumper cable to (**STLINKv2 pin #4**), this will serve as the **Ground** signal (**GND**) |
  49 |         | Attach the FEMALE end of a FEMALE-TO-MALE **GREEN** jumper cable to (**STLINKv2 pin #5**), this will serve as the **Test Data In** signal (**TDI**) |
  50 |         | Attach the FEMALE end of a FEMALE-TO-MALE **BLUE** jumper cable to (**STLINKv2 pin #7**), this will serve as the **Test Mode Select** signal (**TMS**) |
  51 |         | Attach the FEMALE end of a FEMALE-TO-MALE **WHITE** jumper cable to  (**STLINKv2 pin #9**), this will serve as the **Test Clock** signal (**TCK**) |
  52 |         | Attach the FEMALE end of a FEMALE-TO-MALE **YELLOW** jumper cable to (**STLINKv2 pin #13**), this will serve as the **Test Data Out** signal (**TDO**)
  53
  54 Next, we will wire each of the pins on the the FPGA according to the diagrams, tables, and images on this page.
  55
  56 Follow this section if you have the ULX3S FPGA:
  57
  58 | Done?   | Checklist Step |
  59 |---------|----------------|
  60 |         | Attach one end of a FEMALE-TO-FEMALE **RED** jumper cable to (**ULX3S pin #2**), this will serve as the **Voltage Reference** signal (**VREF**)
  61 |         | Attach one end of a FEMALE-TO-FEMALE **BLACK** jumper cable to (**ULX3S pin #4**), this will serve as the **Ground** signal (**GND**) |
  62 |         | Attach one end of a FEMALE-TO-FEMALE **GREEN** jumper cable to (**ULX3S pin #5**), this will serve as the **Test Data In** signal (**TDI**) |
  63 |         | Attach one end of a FEMALE-TO-FEMALE **BLUE** jumper cable to (**ULX3S pin #6**), this will serve as the **Test Mode Select** signal (**TMS**) |
  64 |         | Attach one end of a FEMALE-TO-FEMALE **WHITE** jumper cable to (**ULX3S pin #7**), this will serve as the **Test Clock** signal (**TCK**) |
  65 |         | Attach one end of a FEMALE-TO-FEMALE **YELLOW** jumper cable to (**ULX3S pin #8**), this will serve as the **Test Data Out** signal (**TDO**) |
  66
  67 Follow this section if you have the Versa ECP5 FPGA:
  68
  69 | Done?   | Checklist Step |
  70 |---------|----------------|
  71 |         | Attach one end of a FEMALE-TO-FEMALE **RED** jumper cable to (**X3 pin #39**), this will serve as the **Voltage Reference** signal (**VREF**) |
  72 |         | Attach one end of a FEMALE-TO-FEMALE **BLACK** jumper cable to (**X3 pin #1**), this will serve as the **Ground** signal (**GND**) |
  73 |         | Attach one end of a FEMALE-TO-FEMALE **GREEN** jumper cable to (**X3 pin #4**), this will serve as the **Test Data In** signal (**TDI**) |
  74 |         | Attach one end of a FEMALE-TO-FEMALE **BLUE** jumper cable to (**X3 pin #5**), this will serve as the **Test Mode Select** signal (**TMS**) |
  75 |         | Attach one end of a FEMALE-TO-FEMALE **WHITE** jumper cable to (**X3 pin #6**), this will serve as the **Test Clock** signal (**TCK**) |
  76 |         | Attach one end of a FEMALE-TO-FEMALE **YELLOW** jumper cable to (**X3 pin #7**), this will serve as the **Test Data Out** signal (**TDO**) |
  77
  78 Final steps for both FPGA boards:
  79
  80 | Done?   | Checklist Step |
  81 |---------|----------------|
  82 |         | Check each jumper wire connection between the corresponding pins on the FPGA and the STLINKv2 **THREE** times |
  83 |         | ***lckl*** check for ground loops? |
  84
  85
  86 Finally, we will connect the MALE end of the jumper cable from the STLINKv2 to the FEMALE end of the jumper cable from the FPGA.
  87
  88 | Done?   | Checklist Step |
  89 |---------|----------------|
  90 |         | Attach the MALE end of the **RED** jumper cable from the STLINKv2 cable to the FEMALE end of the **RED** jumper cable from the FPGA. |
  91 |         | Attach the MALE end of the **BLACK** jumper cable from the STLINKv2 cable to the FEMALE end of the **BLACK** jumper cable from the FPGA. |
  92 |         | Attach the MALE end of the **GREEN** jumper cable from the STLINKv2 cable to the FEMALE end of the **GREEN** jumper cable from the FPGA. |
  93 |         | Attach the MALE end of the **BLUE** jumper cable from the STLINKv2 cable to the FEMALE end of the **BLUE** jumper cable from the FPGA. |
  94 |         | Attach the MALE end of the **WHITE** jumper cable from the STLINKv2 cable to the FEMALE end of the **WHITE** jumper cable from the FPGA. |
  95 |         | Attach the MALE end of the **YELLOW** jumper cable from the STLINKv2 cable to the FEMALE end of the **YELLOW** jumper cable from the FPGA. |
  96
  97 ## Connecting the dots:
  98
  99 Accurate render of board for reference <https://github.com/emard/ulx3s/blob/master/pic/ulx3st.jpg>
 100
 101 STLINKV2 Pins and JTAG signals schematic/user guide <https://www.st.com/resource/en/user_manual/dm00026748-stlinkv2-incircuit-debuggerprogrammer-for-stm8-and-stm32-stmicroelectronics.pdf>
 102
 103 Litex platform file <https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py>
 104
 105     ("gpio", 0,
 106         Subsignal"p", Pins("B11")),
 107         Subsignal("n", Pins("C11")),
 108         IOStandard("LVCMOS33")
 109     ),
 110     ("gpio", 1,
 111         Subsignal("p", Pins("A10")),
 112         Subsignal("n", Pins("A11")),
 113         IOStandard("LVCMOS33")
 114     ),
 115
 116 ULX3S FPGA constraints file <https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342>
 117
 118     LOCATE COMP "gp[0]" SITE "B11"; # J1_5+  GP0 PCLK
 119     LOCATE COMP "gn[0]" SITE "C11"; # J1_5-  GN0 PCLK
 120     LOCATE COMP "gp[1]" SITE "A10"; # J1_7+  GP1 PCLK
 121     LOCATE COMP "gn[1]" SITE "A11"; # J1_7-  GN1 PCLK
 122
 123 ULX3S FPGA Schematic <https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf>
 124
 125 ```
 126 J1 J2 PIN number 1-40 is for FEMALE 90° ANGLED header.
 127 For MALE VERTICAL header, SWAP EVEN and ODD pin numbers.
 128
 129                     J1
 130
 131  Label  [GP{x}]|PCB pin label|[GN{x}] Label
 132            (Pin count +)(Pin count -)
 133 _________________V__________V________________
 134  IO VOLT REF 3V3 2  |3.3V|  1  NOT CONNECTED
 135            [GND] 4  | -| |  3  NOT CONNECTED
 136 PCLKT0_0   [GP0] 6  |  0 |  5  [GN0] PCLKC0_0
 137 PCLKT0_1   [GP1] 8  |  1 |  7  [GN1] PCLKC0_1
 138
 139
 140 GP,GN 0-7 single-ended connected to Bank0
 141 GP,GN 8-13 differential bidirectional connected to BANK7
 142 ```
 143
 144 Connecting all the dots:
 145
 146 ```
 147 Board pin # (count) | Board pin label # | FPGA IO PAD | GPIO # (n/p) |   Label  |
 148       5 (J1_5-)     |         0         |      C11    |    gn[0]     | PCLKC0_0 |
 149       6 (J1_5+)     |         0         |      B11    |    gp[0]     | PCLKT0_0 |
 150       7 (J1_7-)     |         1         |      A11    |    gn[1]     | PCLKC0_1 |
 151       8 (J1_7+)     |         1         |      A10    |    gp[1]     | PCLKT0_1 |
 152 ```
 153
 154 As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs.
 155
 156 Proposed FPGA External Pin to STLINK JTAG pin connections:
 157
 158 ```
 159    all pin #'s have headers pins on the fpga unless denoted as (no header)
 160  ______________________________________________________________________________
 161 |             | board |             |             |                |           |
 162 |             | label |             |             |STLINKV2  JTAG  |           |
 163 |    pin #    |   #   | FPGA IO PAD |GPIO # (n/p) | Pin #  (Signal)|Wire Colour|
 164 |_____________|_______|_____________|_____________|________________|___________|
 165 |1 (no header)|  3.3v |NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
 166 |2            |  3.3v | IO VOLT REF | IO VOLT REF |    2 (MCU VDD) |    Red    |
 167 |3 (no header)|-|(GND)|NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
 168 |4            |-|(GND)|    NONE     |     GND     |    4 (GND)     |   Black   |
 169 |5 (J1_5-)    |   0   |     C11     |    gn[0]    |    5 (JTDI)    |   Green   |
 170 |6 (J1_5+)    |   0   |     B11     |    gp[0]    |    7 (JTMS)    |   Blue    |
 171 |7 (J1_7-)    |   1   |     A11     |    gn[1]    |    9 (JTCK)    |   White   |
 172 |8 (J1_7+)    |   1   |     A10     |    gp[1]    |   13 (JTDO)    |   Yellow  |
 173 |_____________|_______|_____________|_____________|________________|___________|
 174 ```
 175
 176 Complete diagram:
 177
 178 ```
 179 Pins intentionally have no header or are not connected to the STLINKVT are marked
 180 and therefore have no value are marked with 'NOT'
 181
 182 (ST# JTAG) = (STLINKV2 pin #   JTAG signal name)
 183
 184
 185                              J1
 186             Wire                             Wire
 187            Colour [GP{x}]|PCB label|[GN{x}] Colour
 188 (ST# JTAG)        (Pin count +)(Pin count -)      (ST# JTAG)
 189  ________________________V__________V_________________________
 190 |                                                             |
 191 |( 2 JVDD) red    [VREF] 2  |3.3V|  1   NOT   NOT    NOT      |
 192 |( 4 JGND) black   [GND] 4  | -| |  3   NOT   NOT    NOT      |
 193 |( 7 JTMS) blue    [GP0] 6  |  0 |  5  [GN0] green (5 JTDI)   |
 194 |(13 JTDO) yellow  [GP1] 8  |  1 |  7  [GN1] white (9 JTCK)   |
 195 |_____________________________________________________________|
 196 ```
 197
 198 ## Images of wires on FPGA and on STLINKV2
 199
 200 Image of JTAG jumper wire connections on ULX3S FPGA side
 201
 202 [[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]]
 203
 204 Image of JTAG jumper wire connections on STLINKV2 side
 205
 206 (same orientation as JTAG pinout documentation)
 207
 208 [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2_same_orientation_as_jtag.jpg size="250x" ]]
 209
 210 Image of JTAG jumper wire connections on STLINKV2 side
 211
 212 (opposite orientation as JTAG pinout documentation,
 213
 214 same orientation as 'ST' text on STLINKV2 device)
 215
 216 [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2_opposite_orientation_to_jtag.jpg size="x302" ]]
 217
 218 # STLinkV2 connector
 219
 220 [[!img 2020-11-03_14-08.png size="900x" ]]
 221
 222 [[!img 2020-11-03_14-09.png size="900x" ]]
 223
 224 # VERSA ECP5 Connections
 225
 226 Table of connections:
 227
 228 | X3  pin #   | FPGA IO PAD | STLinkv2       |Wire Colour|
 229 |-------------|-------------|----------------|-----------|
 230 |39 +3.3V     | 3.3V supply | 2 (MCU VDD)    |   Red     |
 231 |1 GND        | GND         | 4 (GND)        |   Black   |
 232 |4 IO29       |  B19        |    5 (TDI)     |   Green   |
 233 |5 IO30       |  B12        |    7 (TMS)     |   Blue    |
 234 |6 IO31       |  B9         |    9 (TCK)     |   White   |
 235 |7 IO32       |  E6         |   13 (TDO)     |   Yellow  |
 236
 237 [[!img 2020-11-03_13-22.png size="900x" ]]
 238
 239 [[!img 2020-11-03_13-25.png size="900x" ]]
 240
 241 [[!img versa_ecp5_x3_connector.jpg size="900x" ]]