1 # Steps for Hello World Microwatt ls2 for fpga/boards
3 * Currently works for Arty A7-100t, VERSA_ECP5 and in future others
4 * Bugzilla page <https://bugs.libre-soc.org/show_bug.cgi?id=802>
5 * NGI POINTER <https://bugs.libre-soc.org/show_bug.cgi?id=818>
6 * [Bug #1127 - Generating core with SVP64](https://bugs.libre-soc.org/show_bug.cgi?id=1127)
11 git clone https://git.libre-soc.org/git/dev-env-setup.git
14 ./mk-deb-chroot ls2-hello-world
15 ./cp-scripts-to-chroot ls2-hello-world
18 schroot -c ls2-hello-world
19 sudo bash # helps define SUDO_USER in new chroot
22 # install dependencies in new chroot
23 ./install-hdl-apt-reqs
26 ./nextpnr-xilinx-install
29 # if you intend to upload fpga bitstreams in the same chroot, also need
31 ./fpga-boot-load-prog-install
35 # make hello_world.bin from microwatt
39 cp hello_world.bin ../../ls2
42 # make the Libre-SOC core (for external use)
44 make microwatt_external_core
45 cp external_core_top.v ../ls2
47 # check out ls2 peripheral framework
49 git checkout 426e2d9585cd4b1fb96a38987f97878285ee5ba7
51 export PATH=/usr/local/nextpnr-xilinx/bin:$PATH
52 export XRAY_DIR=/usr/local/nextpnr-xilinx
54 # plug in FPGA board (Arty A7-100t, VERSA_ECP5, other)
55 # run in 2nd terminal "minicom -D /dev/ttyUSB1"
57 python3 src/ls2.py arty_a7 hello_world.bin # for Arty A7-100t
58 python3 src/ls2.py versa_ecp5 hello_world.bin # (for a VERSA_ECP5)
60 This directly programs a tmp bitstream using xc3sprog to nexys4 board.
61 If needed modify sources to produce a fixed file bitstream and
63 copy build/top.bit to board/server (scp, rsync)
64 minicom -D /dev/ttyUSB1
65 xc3sprog -c nexys4 top.bit
67 If there are multiple Arty-A7-100t boards connected you need to know
68 the serial number (lsusb | grep Serial)
70 xc3sprog -c nexys4 -s {insert_full_serial_number} top.bit
72 # Using ls2 with microwatt
74 This is doable but tricky. An older version is required at present.
76 git clone https://git.libre-soc.org/git/microwatt.git
77 git checkout microwatt_verilator
80 From there, some hand-editing is required. search for core_NNNNNNN_XXX_YYY
81 and rename it to external_core_top. Save the file as external_core_top.v
82 and it can be used in place of the Libre-SOC Core, above.
84 In fact any core can be used with ls, as long as it is compliant with
85 the interfaces. Both Wishbone Interfaces must be WB4 Pipeline
86 compliant (proper stall handling) or the stall signal faked externally
87 with a wrapper: `stall=stb&~ack`
89 # Using ls2 with verilator
91 first you need to build hello_world (or any other firmware) to start at
92 0xff000000. Then you can run build ls.v using that firmware:
94 python3 src/ls2.py sim /tmp/ff000000_hw.bin
96 The output of that command is:
98 platform sim /tmp/ff000000_hw.bin None
99 fpga sim firmware /tmp/ff000000_hw.bin
103 hyperram pins [<lambdasoc.periph.hyperram.HyperRAMPads object at 0x735e9940dd30>]
104 fw at address ff000000
105 SRAM 0x8000 at address 0x0
107 To use verilator, make sure to run the devscript:
111 And set the GHDLSYNTH and update PATH:
113 export PATH=/usr/local/verilator/bin:$PATH
114 export GHDLSYNTH=ghdl
116 After that you can compile microwatt-verilator:
118 export FPGA_TARGET=verilator
119 make microwatt-verilator
121 # Estimating transistor count using yosys
123 Use yosys to run synthesis and using `stat` to view gate/transistor count:
127 yosys> read_verilog ls2.v external_core_top.v ../uart16550/rtl/verilog/*.v
129 yosys> tee -a stat_cmos.log stat -tech cmos
131 Then you can view the resulting log file afterwards. Bare in mind `synth` will probably take a while. **TODO: Find multi-threaded option**