HDL_workflow/ls2.mdwn

   1 # Steps for Hello World Microwatt ls2 for fpga/boards
   2
   3 * Currently works for Arty A7-100t, VERSA_ECP5 and in future others
   4 * Bugzilla page <https://bugs.libre-soc.org/show_bug.cgi?id=802>
   5 * NGI POINTER  <https://bugs.libre-soc.org/show_bug.cgi?id=818>
   6
   7 # Install Instructions
   8
   9     # devscripts
  10     git clone https://git.libre-soc.org/git/dev-env-setup.git
  11     cd dev-env-setup
  12     sudo bash
  13     ./mk-deb-chroot ls2-hello-world
  14     ./cp-scripts-to-chroot ls2-hello-world
  15     exit # back to user
  16
  17     schroot -c ls2-hello-world
  18     sudo bash # helps define SUDO_USER in new chroot
  19     cd ~/dev-env-setup
  20
  21     # install dependencies in new chroot
  22     ./install-hdl-apt-reqs
  23     ./hdl-dev-repos
  24     ./hdl-tools-yosys
  25     ./nextpnr-xilinx-install
  26     export PATH=/usr/local/nextpnr-xilinx/bin:$PATH
  27     export XRAY_DIR=/usr/local/nextpnr-xilinx
  28     ./hdl-dev-ls2
  29     cd ~/src
  30
  31     # make hello_world.bin from microwatt
  32     cd tercel-qspi/
  33     cd hello_world/
  34     make
  35     cp hello_world.bin ../../ls2
  36     cd ../..
  37
  38     # make the Libre-SOC core (for external use)
  39     cd soc
  40     make microwatt_external_core
  41     cp external_core_top.v ../ls2
  42
  43     # check out ls2 peripheral framework
  44     cd ../ls2
  45     git checkout 426e2d9585cd4b1fb96a38987f97878285ee5ba7
  46
  47     # plug in FPGA board (Arty A7-100t, VERSA_ECP5, other)
  48     # run in 2nd terminal "minicom -D /dev/ttyUSB1"
  49
  50     python3 src/ls2.py arty_a7 hello_world.bin    # for Arty A7-100t
  51     python3 src/ls2.py versa_ecp5 hello_world.bin # (for a VERSA_ECP5)
  52
  53 This directly programs a tmp bitstream using xc3sprog to nexys4 board.
  54 If needed modify sources to produce a fixed file bitstream and
  55
  56     copy build/top.bit to board/server (scp, rsync)
  57     minicom -D /dev/ttyUSB1
  58     xc3sprog -c nexys4 top.bit
  59
  60 # Using ls2 with microwatt
  61
  62 This is doable but tricky.  An older version is required at present.
  63
  64     git clone https://git.libre-soc.org/git/microwatt.git
  65     git checkout microwatt_verilator
  66     make microwatt.v
  67
  68 From there, some hand-editing is required.  search for core_NNNNNNN_XXX_YYY
  69 and rename it to external_core_top. Save the file as external_core_top.v
  70 and it can be used in place of the Libre-SOC Core, above.
  71
  72 In fact any core can be used with ls, as long as it is compliant with
  73 the interfaces.  Both Wishbone Interfaces must be WB4 Pipeline
  74 compliant (proper stall handling) or the stall signal faked externally
  75 with a wrapper: `stall=stb&~ack`
  76
  77 # Using ls2 with verilator
  78
  79 first you need to build hello_world (or any other firmware) to start at
  80 0xff000000. Then you can run build ls.v using that firmware:
  81
  82     python3 src/ls2.py sim /tmp/ff000000_hw.bin
  83
  84 The output of that command is:
  85
  86     platform sim /tmp/ff000000_hw.bin None
  87     fpga sim firmware /tmp/ff000000_hw.bin
  88     ddr pins None
  89     spiflash pins None
  90     ethmac pins None
  91     hyperram pins [<lambdasoc.periph.hyperram.HyperRAMPads object at 0x735e9940dd30>]
  92     fw at address ff000000
  93     SRAM 0x8000 at address 0x0
  94
  95 After that you can compile microwatt-verilator:
  96
  97         export FPGA_TARGET=verilator
  98         make microwatt-verilator