HDL_workflow/ls2.mdwn

   1 # Steps for Hello World Microwatt ls2 for fpga/boards
   2
   3 * Currently works for Arty A7-100t, VERSA_ECP5 and in future others
   4 * Bugzilla page <https://bugs.libre-soc.org/show_bug.cgi?id=802>
   5 * NGI POINTER  <https://bugs.libre-soc.org/show_bug.cgi?id=818>
   6 * [Bug #1127 - Generating core with SVP64](https://bugs.libre-soc.org/show_bug.cgi?id=1127)
   7
   8 # Install Instructions
   9
  10     # devscripts
  11     git clone https://git.libre-soc.org/git/dev-env-setup.git
  12     cd dev-env-setup
  13     sudo bash
  14     ./mk-deb-chroot ls2-hello-world
  15     ./cp-scripts-to-chroot ls2-hello-world
  16     exit # back to user
  17
  18     schroot -c ls2-hello-world
  19     sudo bash # helps define SUDO_USER in new chroot
  20     cd ~/dev-env-setup
  21
  22     # install dependencies in new chroot
  23     ./install-hdl-apt-reqs
  24     ./hdl-dev-repos
  25     ./hdl-tools-yosys
  26     ./nextpnr-xilinx-install
  27     export PATH=/usr/local/nextpnr-xilinx/bin:$PATH
  28     export XRAY_DIR=/usr/local/nextpnr-xilinx
  29     ./hdl-dev-ls2
  30     ./fpga-boot-load-prog-install
  31     cd ~/src
  32
  33     # make hello_world.bin from microwatt
  34     cd tercel-qspi/
  35     cd hello_world/
  36     make
  37     cp hello_world.bin ../../ls2
  38     cd ../..
  39
  40     # make the Libre-SOC core (for external use)
  41     cd soc
  42     make microwatt_external_core
  43     cp external_core_top.v ../ls2
  44
  45     # check out ls2 peripheral framework
  46     cd ../ls2
  47     git checkout 426e2d9585cd4b1fb96a38987f97878285ee5ba7
  48
  49     # plug in FPGA board (Arty A7-100t, VERSA_ECP5, other)
  50     # run in 2nd terminal "minicom -D /dev/ttyUSB1"
  51
  52     python3 src/ls2.py arty_a7 hello_world.bin    # for Arty A7-100t
  53     python3 src/ls2.py versa_ecp5 hello_world.bin # (for a VERSA_ECP5)
  54
  55 This directly programs a tmp bitstream using xc3sprog to nexys4 board.
  56 If needed modify sources to produce a fixed file bitstream and
  57
  58     copy build/top.bit to board/server (scp, rsync)
  59     minicom -D /dev/ttyUSB1
  60     xc3sprog -c nexys4 top.bit
  61
  62 If there are multiple Arty-A7-100t boards connected you need to know
  63 the serial number (lsusb | grep Serial)
  64
  65     xc3sprog -c nexys4 -s {insert_full_serial_number} top.bit
  66
  67 # Using ls2 with microwatt
  68
  69 This is doable but tricky.  An older version is required at present.
  70
  71     git clone https://git.libre-soc.org/git/microwatt.git
  72     git checkout microwatt_verilator
  73     make microwatt.v
  74
  75 From there, some hand-editing is required.  search for core_NNNNNNN_XXX_YYY
  76 and rename it to external_core_top. Save the file as external_core_top.v
  77 and it can be used in place of the Libre-SOC Core, above.
  78
  79 In fact any core can be used with ls, as long as it is compliant with
  80 the interfaces.  Both Wishbone Interfaces must be WB4 Pipeline
  81 compliant (proper stall handling) or the stall signal faked externally
  82 with a wrapper: `stall=stb&~ack`
  83
  84 # Using ls2 with verilator
  85
  86 first you need to build hello_world (or any other firmware) to start at
  87 0xff000000. Then you can run build ls.v using that firmware:
  88
  89     python3 src/ls2.py sim /tmp/ff000000_hw.bin
  90
  91 The output of that command is:
  92
  93     platform sim /tmp/ff000000_hw.bin None
  94     fpga sim firmware /tmp/ff000000_hw.bin
  95     ddr pins None
  96     spiflash pins None
  97     ethmac pins None
  98     hyperram pins [<lambdasoc.periph.hyperram.HyperRAMPads object at 0x735e9940dd30>]
  99     fw at address ff000000
 100     SRAM 0x8000 at address 0x0
 101
 102 To use verilator, make sure to run the devscript:
 103
 104     ./verilator-install
 105
 106 And set the GHDLSYNTH and update PATH:
 107
 108     export PATH=/usr/local/verilator/bin:$PATH
 109     export GHDLSYNTH=ghdl
 110
 111 After that you can compile microwatt-verilator:
 112
 113         export FPGA_TARGET=verilator
 114         make microwatt-verilator
 115
 116 # Estimating transistor count using yosys
 117
 118 Use yosys to run synthesis and using `stat` to view gate/transistor count:
 119
 120     cd src/ls2/
 121     yosys
 122     yosys> read_verilog ls2.v external_core_top.v ../uart16550/rtl/verilog/*.v
 123     yosys> synth
 124     yosys> tee -a stat_cmos.log stat -tech cmos
 125
 126 Then you can view the resulting log file afterwards. Bare in mind `synth` will probably take a while. **TODO: Find multi-threaded option**