arch-riscv: Fix disassembling for atomic instructions
[gem5.git] / MAINTAINERS
1 See CONTRIBUTING.md for details of gem5's contribution process.
2
3 This file contains the keywords used in commit messages. Each keyword has one
4 or more maintainers. At least one (not all) of these maintainers must review
5 the patch before it can be pushed. These people will automatically be emailed
6 when you upload the patch to Gerrit (https://gem5-review.googlesource.com).
7 These keywords mostly follow the directory structure.
8
9 Individuals on the project management committee are maintainers for all of the
10 gem5 components (i.e., they can review any patch as the maintainer). These
11 individuals are required to review any patches to components without explicit
12 maintainers.
13
14 PMC Members (general maintainers):
15 Ali Saidi <asaidi@gmail.com>
16 Andreas Sandberg <andreas.sandberg@arm.com>
17 Brad Beckmann <brad.beckmann@amd.com>
18 David Wood <david@cs.wisc.edu>
19 Gabe Black <gabeblack@google.com>
20 Jason Lowe-Power <jason@lowepower.com> (chair)
21 Matt Sinclair <sinclair@cs.wisc.edu>
22 Tony Gutierrez <anthony.gutierrez@amd.com>
23 Steve Reinhardt <stever@gmail.com>
24
25 arch: General architecture-specific components
26 Gabe Black <gabeblack@google.com>
27 arch-alpha:
28 arch-arm:
29 Andreas Sandberg <andreas.sandberg@arm.com>
30 Giacomo Travaglini <giacomo.travaglini@arm.com>
31 arch-hsail:
32 Tony Gutierrez <anthony.gutierrez@amd.com>
33 arch-mips:
34 arch-power:
35 arch-riscv:
36 Alec Roelke <ar4jc@virginia.edu>
37 arch-sparc:
38 Gabe Black <gabeblack@google.com>
39 arch-x86:
40 Gabe Black <gabeblack@google.com>
41
42 base:
43
44 configs:
45 Jason Lowe-Power <jason@lowepower.com>
46
47 cpu: General changes to all CPU models (e.g., BaseCPU)
48 cpu-kvm:
49 Andreas Sandberg <andreas.sandberg@arm.com>
50 cpu-minor:
51 cpu-o3:
52 cpu-simple:
53
54 dev:
55 dev-virtio:
56 Andreas Sandberg <andreas.sandberg@arm.com>
57
58 dev-arm:
59 Andreas Sandberg <andreas.sandberg@arm.com>
60 Giacomo Travaglini <giacomo.travaglini@arm.com>
61
62 ext: Components external to gem5
63
64 gpu-compute:
65 Tony Gutierrez <anthony.gutierrez@amd.com>
66
67 learning-gem5: The code and configs for the Learning gem5 book (see
68 learning.gem5.com)
69 Jason Lowe-Power <jason@lowepower.com>
70
71 mem: General memory system (e.g., XBar, Packet)
72 Nikos Nikoleris <nikos.nikoleris@arm.com>
73 mem-cache: Classic caches and coherence
74 Nikos Nikoleris <nikos.nikoleris@arm.com>
75 mem-garnet: Garnet subcomponent of Ruby
76 Tushar Krishna <tushar@ece.gatech.edu>
77 mem-ruby: Ruby structures and protocols
78 Brad Beckmann <brad.beckmann@amd.com>
79 Jason Lowe-Power <jason@lowepower.com>
80
81 misc: Anything outside of the other categories
82
83 python: Python SimObject wrapping and infrastructure
84 Andreas Sandberg <andreas.sandberg@arm.com>
85
86 scons: Build system
87
88 sim: General simulation components
89 Jason Lowe-Power <jason@lowepower.com>
90 sim-se: Syscall emulation
91 Brandon Potter <brandon.potter@amd.com>
92 sim-power: Power modeling
93 Andreas Sandberg <andreas.sandberg@arm.com>
94
95 stats: Updates to statistics for regressions
96
97 system: System boot code and related components
98 system-alpha:
99 system-arm:
100 Andreas Sandberg <andreas.sandberg@arm.com>
101 Giacomo Travaglini <giacomo.travaglini@arm.com>
102
103 systemc: Code for the gem5 SystemC implementation and interface
104 Gabe Black <gabeblack@google.com>
105
106 tests: testing changes (not stats updates for tests. See stats:)
107 Bobby Bruce <bbruce@ucdavis.edu>
108
109 util: